Logic BIST architecture using staggered launch-on-shift for testing designs containing asynchronous clock domains

Shianling Wu, Laung Terng Wang, Lizhen Yu, Hiroshi Furukawa, Xiaoqing Wen, Wen Ben Jone, Nur A. Touba, Feifei Zhao, Jinsong Liu, Hao Jan Chao, Fangfang Li, Zhigang Jiang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

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Engineering & Materials Science