Logic design system with evaluation‐redesign mechanism

Fumihiro Maruyama, Taeko Kakuda, Yusuke Matsunaga, Nobuaki Kawato, Yoriko Minoda, Shuho Sawada

Research output: Contribution to journalArticle

Abstract

Sophisticated CAD (Computer‐Aided Design) systems that can produce quality designs quickly are anticipated to keep pace with the remarkable advance of VLSI technology. This paper presents a cooperative logic design system, co‐LODEX, in the two streams of design, datapath design and control design. The feature of co‐LODEX is its evaluation‐redesign mechanism using assumption‐based reasoning, which automates the evaluate‐redesign cycle under constraints. As constraints co‐LODEX takes those on area and speed. Design alternatives are considered as assumptions and constraint violations as contradictions. Redesign was implemented as contraction resolution. Here, justifications are defined for constraint violations whose forms are independent of actual constraint values, and the evaluation‐redesign mechanism based on these justifications is described. An experimental system was implemented and it was observed that it could correctly carry out the evaluation‐redesign mechanism. It enables the user to specify constraints in terms of numbers and obtain a circuit satisfying all of them. It also allows the user to obtain a variety of circuits efficiently with different characteristics conforming to the same specification by changing constraints.

Original languageEnglish
Pages (from-to)105-113
Number of pages9
JournalElectronics and Communications in Japan (Part III: Fundamental Electronic Science)
Volume73
Issue number5
DOIs
Publication statusPublished - Jan 1 1990
Externally publishedYes

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Logic design
Networks (circuits)
Specifications

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Logic design system with evaluation‐redesign mechanism. / Maruyama, Fumihiro; Kakuda, Taeko; Matsunaga, Yusuke; Kawato, Nobuaki; Minoda, Yoriko; Sawada, Shuho.

In: Electronics and Communications in Japan (Part III: Fundamental Electronic Science), Vol. 73, No. 5, 01.01.1990, p. 105-113.

Research output: Contribution to journalArticle

Maruyama, Fumihiro ; Kakuda, Taeko ; Matsunaga, Yusuke ; Kawato, Nobuaki ; Minoda, Yoriko ; Sawada, Shuho. / Logic design system with evaluation‐redesign mechanism. In: Electronics and Communications in Japan (Part III: Fundamental Electronic Science). 1990 ; Vol. 73, No. 5. pp. 105-113.
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