Low noise-low power digital phase-locked loop

M. Saber, Yutaka Jitsumatsu, M. T.A. Khan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

We propose a phase-locked loop (PLL) architecture, which reduces the double frequency ripple without increasing the order of loop filter. Proposed architecture uses quadrature numerically-controlled oscillator (NCO) to provide two output signals with phase difference of π/2. One of them is subtracted from the input signal before multiplying with the other output of NCO. The system also provides stability in case the input signal has noise in amplitude or phase. The proposed structure is implemented using field programmable gate array (FPGA), which dissipates 15.44mw and works at clock frequency of 155.8 MHz.

Original languageEnglish
Title of host publicationTENCON 2010 - 2010 IEEE Region 10 Conference
Pages1324-1329
Number of pages6
DOIs
Publication statusPublished - Dec 1 2010
Event2010 IEEE Region 10 Conference, TENCON 2010 - Fukuoka, Japan
Duration: Nov 21 2010Nov 24 2010

Publication series

NameIEEE Region 10 Annual International Conference, Proceedings/TENCON

Other

Other2010 IEEE Region 10 Conference, TENCON 2010
CountryJapan
CityFukuoka
Period11/21/1011/24/10

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

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    Saber, M., Jitsumatsu, Y., & Khan, M. T. A. (2010). Low noise-low power digital phase-locked loop. In TENCON 2010 - 2010 IEEE Region 10 Conference (pp. 1324-1329). [5685954] (IEEE Region 10 Annual International Conference, Proceedings/TENCON). https://doi.org/10.1109/TENCON.2010.5685954