Low-temperature 3D chip-stacking using compliant bump

Naoya Watanabe, Takamichi Mori, Tanemasa Asano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

We demonstrate low-temperature 3D chip-stacking (number of bumps: 25,200, bump size / bump pitch: 11μm /20 μm, chip-stacking temperature: 30°C) using the compliant bump. Low-temperature 3D chip-stacking was carried out by mechanical caulking using compliant bump and doughnut-shaped electrode. This method is very effective in realizing 3D chip-stacking even at room temperature.

Original languageEnglish
Title of host publication10th Electronics Packaging Technology Conference, EPTC 2008
Pages393-398
Number of pages6
DOIs
Publication statusPublished - 2008
Event10th Electronics Packaging Technology Conference, EPTC 2008 - Singapore, Singapore
Duration: Dec 9 2008Dec 12 2008

Other

Other10th Electronics Packaging Technology Conference, EPTC 2008
CountrySingapore
CitySingapore
Period12/9/0812/12/08

    Fingerprint

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Watanabe, N., Mori, T., & Asano, T. (2008). Low-temperature 3D chip-stacking using compliant bump. In 10th Electronics Packaging Technology Conference, EPTC 2008 (pp. 393-398). [4763466] https://doi.org/10.1109/EPTC.2008.4763466