Low-temperature 3D chip-stacking using compliant bump

Naoya Watanabe; Takamichi Mori; Tanemasa Asano

doi:10.1109/EPTC.2008.4763466

Low-temperature 3D chip-stacking using compliant bump

Naoya Watanabe, Takamichi Mori, Tanemasa Asano

Integrated Electronic Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

We demonstrate low-temperature 3D chip-stacking (number of bumps: 25,200, bump size / bump pitch: 11μm /20 μm, chip-stacking temperature: 30°C) using the compliant bump. Low-temperature 3D chip-stacking was carried out by mechanical caulking using compliant bump and doughnut-shaped electrode. This method is very effective in realizing 3D chip-stacking even at room temperature.

Original language	English
Title of host publication	10th Electronics Packaging Technology Conference, EPTC 2008
Pages	393-398
Number of pages	6
DOIs	https://doi.org/10.1109/EPTC.2008.4763466
Publication status	Published - 2008
Event	10th Electronics Packaging Technology Conference, EPTC 2008 - Singapore, Singapore Duration: Dec 9 2008 → Dec 12 2008

Other

Other	10th Electronics Packaging Technology Conference, EPTC 2008
Country/Territory	Singapore
City	Singapore
Period	12/9/08 → 12/12/08

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/EPTC.2008.4763466

Cite this

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title = "Low-temperature 3D chip-stacking using compliant bump",

abstract = "We demonstrate low-temperature 3D chip-stacking (number of bumps: 25,200, bump size / bump pitch: 11μm /20 μm, chip-stacking temperature: 30°C) using the compliant bump. Low-temperature 3D chip-stacking was carried out by mechanical caulking using compliant bump and doughnut-shaped electrode. This method is very effective in realizing 3D chip-stacking even at room temperature.",

author = "Naoya Watanabe and Takamichi Mori and Tanemasa Asano",

year = "2008",

doi = "10.1109/EPTC.2008.4763466",

language = "English",

isbn = "9781424421183",

pages = "393--398",

booktitle = "10th Electronics Packaging Technology Conference, EPTC 2008",

note = "10th Electronics Packaging Technology Conference, EPTC 2008 ; Conference date: 09-12-2008 Through 12-12-2008",

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TY - GEN

T1 - Low-temperature 3D chip-stacking using compliant bump

AU - Watanabe, Naoya

AU - Mori, Takamichi

AU - Asano, Tanemasa

PY - 2008

Y1 - 2008

N2 - We demonstrate low-temperature 3D chip-stacking (number of bumps: 25,200, bump size / bump pitch: 11μm /20 μm, chip-stacking temperature: 30°C) using the compliant bump. Low-temperature 3D chip-stacking was carried out by mechanical caulking using compliant bump and doughnut-shaped electrode. This method is very effective in realizing 3D chip-stacking even at room temperature.

AB - We demonstrate low-temperature 3D chip-stacking (number of bumps: 25,200, bump size / bump pitch: 11μm /20 μm, chip-stacking temperature: 30°C) using the compliant bump. Low-temperature 3D chip-stacking was carried out by mechanical caulking using compliant bump and doughnut-shaped electrode. This method is very effective in realizing 3D chip-stacking even at room temperature.

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U2 - 10.1109/EPTC.2008.4763466

DO - 10.1109/EPTC.2008.4763466

M3 - Conference contribution

AN - SCOPUS:63049118006

SN - 9781424421183

SP - 393

EP - 398

BT - 10th Electronics Packaging Technology Conference, EPTC 2008

T2 - 10th Electronics Packaging Technology Conference, EPTC 2008

Y2 - 9 December 2008 through 12 December 2008

ER -

Low-temperature 3D chip-stacking using compliant bump

Abstract

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All Science Journal Classification (ASJC) codes

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