Low-temperature 3D chip-stacking using compliant bump

Naoya Watanabe, Takamichi Mori, Tanemasa Asano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)


We demonstrate low-temperature 3D chip-stacking (number of bumps: 25,200, bump size / bump pitch: 11μm /20 μm, chip-stacking temperature: 30°C) using the compliant bump. Low-temperature 3D chip-stacking was carried out by mechanical caulking using compliant bump and doughnut-shaped electrode. This method is very effective in realizing 3D chip-stacking even at room temperature.

Original languageEnglish
Title of host publication10th Electronics Packaging Technology Conference, EPTC 2008
Number of pages6
Publication statusPublished - 2008
Event10th Electronics Packaging Technology Conference, EPTC 2008 - Singapore, Singapore
Duration: Dec 9 2008Dec 12 2008


Other10th Electronics Packaging Technology Conference, EPTC 2008

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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