Abstract
We demonstrate low-temperature 3D chip-stacking (number of bumps: 25,200, bump size / bump pitch: 11μm /20 μm, chip-stacking temperature: 30°C) using the compliant bump. Low-temperature 3D chip-stacking was carried out by mechanical caulking using compliant bump and doughnut-shaped electrode. This method is very effective in realizing 3D chip-stacking even at room temperature.
Original language | English |
---|---|
Title of host publication | 10th Electronics Packaging Technology Conference, EPTC 2008 |
Pages | 393-398 |
Number of pages | 6 |
DOIs | |
Publication status | Published - 2008 |
Event | 10th Electronics Packaging Technology Conference, EPTC 2008 - Singapore, Singapore Duration: Dec 9 2008 → Dec 12 2008 |
Other
Other | 10th Electronics Packaging Technology Conference, EPTC 2008 |
---|---|
Country/Territory | Singapore |
City | Singapore |
Period | 12/9/08 → 12/12/08 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering