LOW TEMPERATURE FABRICATION OF SOI-MOSFET'S IN Si/CaF//2/Si HETEROEPITAXIAL STRUCTURES.

Tanemasa Asano, Shinichi Wakabayashi, Hiroshi Ishiwara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The epitaxial growth of Si films on CaF//2/Si heteroepitaxial structures and characteristics of MOSFET's fabricated in the Si/CaF//2/Si structures are investigated. Both the growth of the Si/CaF//2/Si structures and the fabrication of MOSFET's are performed at temperatures below 800 degree C. For the growth of Si films, a new growth method, which involves in situ deposition of a thin ( less than equivalent to 10nm) Si onto the CaF//2 surface at room temperature prior to deposition of Si at elevated temperatures, has been developed in order to prevent interfacial reaction between deposited Si and underlying CaF//2. Al gate n-channel MOSFET's, which are electrically isolated from the substrates, have been fabricated by utilizing plasma enhanced CVD SiO//2 as the gate insulator. The maximum field effect mobility of about 180 cm**2/V multiplied by (times) s has been obtained.

Original languageEnglish
Title of host publicationConference on Solid State Devices and Materials
PublisherBusiness Cent for Academic Soc Japan
Pages519-522
Number of pages4
ISBN (Print)4930813077
Publication statusPublished - Dec 1 1984
Externally publishedYes

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All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Asano, T., Wakabayashi, S., & Ishiwara, H. (1984). LOW TEMPERATURE FABRICATION OF SOI-MOSFET'S IN Si/CaF//2/Si HETEROEPITAXIAL STRUCTURES. In Conference on Solid State Devices and Materials (pp. 519-522). Business Cent for Academic Soc Japan.