Low-temperature high-density chip-stack interconnection using compliant bump

Naoya Watanabe; Tanemasa Asano

doi:10.1109/ECTC.2007.373861

Low-temperature high-density chip-stack interconnection using compliant bump

Naoya Watanabe, Tanemasa Asano

Integrated Electronic Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

12 Citations (Scopus)

Abstract

We demonstrate low-temperature high-density chip-stack interconnection using compliant bump. Low temperature chip stacking was carried out by two methods; (1) plasma cleaning of compliant bumps, (2) mechanical caulking using compliant bump and doughnut-shaped electrode. The latter method is very effective in realizing chip stacking even at room temperature.

Original language	English
Title of host publication	Proceedings - 57th Electronic Components and Technology Conference 2007, ECTC '07
Pages	622-626
Number of pages	5
DOIs	https://doi.org/10.1109/ECTC.2007.373861
Publication status	Published - Oct 22 2007
Event	57th Electronic Components and Technology Conference 2007, ECTC '07 - Sparks, NV, United States Duration: May 29 2007 → Jun 1 2007

Other

Other	57th Electronic Components and Technology Conference 2007, ECTC '07
Country	United States
City	Sparks, NV
Period	5/29/07 → 6/1/07

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All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

Watanabe, N., & Asano, T. (2007). Low-temperature high-density chip-stack interconnection using compliant bump. In Proceedings - 57th Electronic Components and Technology Conference 2007, ECTC '07 (pp. 622-626). [4249947] https://doi.org/10.1109/ECTC.2007.373861

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Access to Document

10.1109/ECTC.2007.373861