Low-temperature high-density chip-stack interconnection using compliant bump

Naoya Watanabe, Tanemasa Asano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

We demonstrate low-temperature high-density chip-stack interconnection using compliant bump. Low temperature chip stacking was carried out by two methods; (1) plasma cleaning of compliant bumps, (2) mechanical caulking using compliant bump and doughnut-shaped electrode. The latter method is very effective in realizing chip stacking even at room temperature.

Original languageEnglish
Title of host publicationProceedings - 57th Electronic Components and Technology Conference 2007, ECTC '07
Pages622-626
Number of pages5
DOIs
Publication statusPublished - Oct 22 2007
Event57th Electronic Components and Technology Conference 2007, ECTC '07 - Sparks, NV, United States
Duration: May 29 2007Jun 1 2007

Other

Other57th Electronic Components and Technology Conference 2007, ECTC '07
CountryUnited States
CitySparks, NV
Period5/29/076/1/07

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All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Watanabe, N., & Asano, T. (2007). Low-temperature high-density chip-stack interconnection using compliant bump. In Proceedings - 57th Electronic Components and Technology Conference 2007, ECTC '07 (pp. 622-626). [4249947] https://doi.org/10.1109/ECTC.2007.373861