LP based cell selection with constraints of timing, area, and power consumption

Yutaka Tamiya, Yusuke Matsunaga, Masahiro Fujita

Research output: Contribution to journalArticle

11 Citations (Scopus)

Abstract

This paper presents a new LP based optimal cell selection method. Optimal cell selection is useful tool for final tuning of LSI designs. It replaces drivabilities of cells, adjusting timing, area, and power constraints. Using the latest and earliest arrival times, it can handle both setup and hold time constraints. We also make an efficient initial basis, which speeds up a simplex LP solver by 5 times without any relaxations nor approximations. From experimental results, it reduces the clock cycle of a manual designed 13k-transistor chip by 17% without any increase of area.

Original languageEnglish
Pages (from-to)378-381
Number of pages4
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication statusPublished - 1994
Externally publishedYes

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Clocks
Transistors
Electric power utilization
Tuning

All Science Journal Classification (ASJC) codes

  • Computational Theory and Mathematics
  • Computer Science Applications
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

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