Memory-constrained implementation of lattice-based encryption scheme on standard Java Card

Ye Yuan, Kazuhide Fukushima, Shinsaku Kiyomoto, Tsuyoshi Takagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

Since NSA announced the plans for transitioning to the algorithms which are resistant to attacks by the potential quantum computers, the interest of implementation of post-quantum cryptography (PQC) on various devices has emerged. Including widely used Java Card, memory-constrained smart cards need the efficient implementation of encryption schemes to resist quantum-computing attacks. Meanwhile, lattice-based cryptography, as one of the strongest candidates for PQC, has attracted wide attention due to their applicability and operating efficiency in recent years. However, due to the limited memory resources and computing power, long integer multiplication is a challenge on Java Card, and it had been considered that only a few lattice-based cryptosystems are fitting into such devices. In this paper, we show the first implementation of a lattice-based encryption scheme on standard Java Card whose running time is nearly optimal (about 100 seconds in decryption for 128-bit security) by combining the use of iterative fast Fourier transform and improved Montgomery modular multiplication. More importantly, we indicate that polynomial multiplication and over signed 15-bit integer arithmetic can be performed on Java Card even if the long integers are not supported, which makes running more lattice-based protocols on Java Card achievable.

Original languageEnglish
Title of host publicationProceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages47-50
Number of pages4
ISBN (Electronic)9781538639283
DOIs
Publication statusPublished - Jun 16 2017
Event10th IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2017 - McLean, United States
Duration: May 1 2017May 5 2017

Publication series

NameProceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2017

Other

Other10th IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2017
CountryUnited States
CityMcLean
Period5/1/175/5/17

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality

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