Memory-CPU size optimization for embedded system designs

Barry Shackleford, Mitsuhiro Yasuda, Etsuko Okushi, Hisao Koizumi, Hiroyuki Tomiyama, Hiroto Yasuura

Research output: Contribution to journalConference article

16 Citations (Scopus)

Abstract

Entire systems embedded in a chip and consisting of a processor, memory, and system-specific peripheral hardware are now commonly contained in commodity electronic devices. Cost minimization of these systems is of paramount economic importance to manufactures of these devices. By employing a variable configuration processor in conjunction with a multi-precision compiler generator there are situations in which considerable system cost reduction can be obtained by synthesizing a CPU that is narrower than the largest variable in the application program.

Original languageEnglish
Pages (from-to)246-251
Number of pages6
JournalProceedings - Design Automation Conference
Publication statusPublished - Jan 1 1997
Externally publishedYes
EventProceedings of the 1997 34th Design Automation Conference - Anaheim, CA, USA
Duration: Jun 9 1997Jun 13 1997

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All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering

Cite this

Shackleford, B., Yasuda, M., Okushi, E., Koizumi, H., Tomiyama, H., & Yasuura, H. (1997). Memory-CPU size optimization for embedded system designs. Proceedings - Design Automation Conference, 246-251.