Module selection using manufacturing information

Hiroyuki Tomiyama, Hiroto Yasuura

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Since manufacturing processes inherently fluctuate, LSI chips which are produced from the same design have different propagation delays. However, the difference in delays caused by the the process fluctuation has rarely been considered in most high-level synthesis systems which were developed before. This paper presents a new approach to module selection in high-level synthesis, which exploits difference in functional unit delays. First, a module library model which assumes the probabilistic nature of functional unit delays is presented. Then, we propose a module selection problem and an algorithm which minimizes the cost per faultless chip. Experimental results demonstrate that the proposed algorithm finds the optimal module selection which would not have been explored without manufacturing information.

Original languageEnglish
Pages (from-to)275-281
Number of pages7
JournalProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Publication statusPublished - 1998

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High level synthesis

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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Module selection using manufacturing information. / Tomiyama, Hiroyuki; Yasuura, Hiroto.

In: Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 1998, p. 275-281.

Research output: Contribution to journalArticle

@article{63c941f4b2c84abb909d5a8233707def,
title = "Module selection using manufacturing information",
abstract = "Since manufacturing processes inherently fluctuate, LSI chips which are produced from the same design have different propagation delays. However, the difference in delays caused by the the process fluctuation has rarely been considered in most high-level synthesis systems which were developed before. This paper presents a new approach to module selection in high-level synthesis, which exploits difference in functional unit delays. First, a module library model which assumes the probabilistic nature of functional unit delays is presented. Then, we propose a module selection problem and an algorithm which minimizes the cost per faultless chip. Experimental results demonstrate that the proposed algorithm finds the optimal module selection which would not have been explored without manufacturing information.",
author = "Hiroyuki Tomiyama and Hiroto Yasuura",
year = "1998",
language = "English",
pages = "275--281",
journal = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

}

TY - JOUR

T1 - Module selection using manufacturing information

AU - Tomiyama, Hiroyuki

AU - Yasuura, Hiroto

PY - 1998

Y1 - 1998

N2 - Since manufacturing processes inherently fluctuate, LSI chips which are produced from the same design have different propagation delays. However, the difference in delays caused by the the process fluctuation has rarely been considered in most high-level synthesis systems which were developed before. This paper presents a new approach to module selection in high-level synthesis, which exploits difference in functional unit delays. First, a module library model which assumes the probabilistic nature of functional unit delays is presented. Then, we propose a module selection problem and an algorithm which minimizes the cost per faultless chip. Experimental results demonstrate that the proposed algorithm finds the optimal module selection which would not have been explored without manufacturing information.

AB - Since manufacturing processes inherently fluctuate, LSI chips which are produced from the same design have different propagation delays. However, the difference in delays caused by the the process fluctuation has rarely been considered in most high-level synthesis systems which were developed before. This paper presents a new approach to module selection in high-level synthesis, which exploits difference in functional unit delays. First, a module library model which assumes the probabilistic nature of functional unit delays is presented. Then, we propose a module selection problem and an algorithm which minimizes the cost per faultless chip. Experimental results demonstrate that the proposed algorithm finds the optimal module selection which would not have been explored without manufacturing information.

UR - http://www.scopus.com/inward/record.url?scp=0032218665&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032218665&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0032218665

SP - 275

EP - 281

JO - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

JF - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

ER -