Multi-level logic minimization across latch boundaries

Yusuke Matsunaga, Masahiro Fujita, Taeko Kakuda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A method to minimize sequential circuits is presented. It uses permissible functions extended for sequential circuits, and can make use of don't cares derived from network topology. Also, an efficient binary decision diagram (BDD) implementation of the extended permissible functions is presented by introducing edge attributes that indicate time label to the BDD. Circuits including latches can be efficiently minimized with the proposed method.

Original languageEnglish
Title of host publication1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers
PublisherPubl by IEEE
Pages406-409
Number of pages4
ISBN (Print)0818620552
Publication statusPublished - Dec 1 1990
Externally publishedYes
Event1990 IEEE International Conference on Computer-Aided Design - ICCAD-90 - Santa Clara, CA, USA
Duration: Nov 11 1990Nov 15 1990

Publication series

Name1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers

Other

Other1990 IEEE International Conference on Computer-Aided Design - ICCAD-90
CitySanta Clara, CA, USA
Period11/11/9011/15/90

    Fingerprint

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Matsunaga, Y., Fujita, M., & Kakuda, T. (1990). Multi-level logic minimization across latch boundaries. In 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers (pp. 406-409). (1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers). Publ by IEEE.