TY - GEN
T1 - Multi-level logic minimization across latch boundaries
AU - Matsunaga, Yusuke
AU - Fujita, Masahiro
AU - Kakuda, Taeko
PY - 1990/12/1
Y1 - 1990/12/1
N2 - A method to minimize sequential circuits is presented. It uses permissible functions extended for sequential circuits, and can make use of don't cares derived from network topology. Also, an efficient binary decision diagram (BDD) implementation of the extended permissible functions is presented by introducing edge attributes that indicate time label to the BDD. Circuits including latches can be efficiently minimized with the proposed method.
AB - A method to minimize sequential circuits is presented. It uses permissible functions extended for sequential circuits, and can make use of don't cares derived from network topology. Also, an efficient binary decision diagram (BDD) implementation of the extended permissible functions is presented by introducing edge attributes that indicate time label to the BDD. Circuits including latches can be efficiently minimized with the proposed method.
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M3 - Conference contribution
AN - SCOPUS:0025558561
SN - 0818620552
T3 - 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers
SP - 406
EP - 409
BT - 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers
PB - Publ by IEEE
T2 - 1990 IEEE International Conference on Computer-Aided Design - ICCAD-90
Y2 - 11 November 1990 through 15 November 1990
ER -