Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs

Masahiro Fujita, Yusuke Matsunaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

The authors present a method for multilevel logic minimization which is particularly suitable for the minimization of look-up table type FPGAs (field programmable gate arrays). Given a set of nodes to be minimized, one first calculates sets of supports which are necessary to construct the functions for the given nodes by applying functional reduction. The functional reduction process guarantees that one can get the minimal support for each node. One then makes a covering table for the set of nodes to be minimized so that one can get the minimal supports to cover all the functions for the given set of nodes to be minimized. The authors present a preliminary implementation and its results for ISCAS combinational benchmark circuits combined with MIS2.1 standard script and a Boolean resubstitution minimizer, and show the effectiveness of the presented method.

Original languageEnglish
Title of host publication1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers
PublisherPubl by IEEE
Pages560-563
Number of pages4
ISBN (Print)0818621575
Publication statusPublished - 1992
Externally publishedYes
Event1991 IEEE International Conference on Computer-Aided Design - ICCAD-91 - Santa Clara, CA, USA
Duration: Nov 11 1991Nov 14 1991

Other

Other1991 IEEE International Conference on Computer-Aided Design - ICCAD-91
CitySanta Clara, CA, USA
Period11/11/9111/14/91

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Fujita, M., & Matsunaga, Y. (1992). Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs. In 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers (pp. 560-563). Publ by IEEE.