Abstract
The authors present a method for multilevel logic minimization which is particularly suitable for the minimization of look-up table type FPGAs (field programmable gate arrays). Given a set of nodes to be minimized, one first calculates sets of supports which are necessary to construct the functions for the given nodes by applying functional reduction. The functional reduction process guarantees that one can get the minimal support for each node. One then makes a covering table for the set of nodes to be minimized so that one can get the minimal supports to cover all the functions for the given set of nodes to be minimized. The authors present a preliminary implementation and its results for ISCAS combinational benchmark circuits combined with MIS2.1 standard script and a Boolean resubstitution minimizer, and show the effectiveness of the presented method.
| Original language | English |
|---|---|
| Title of host publication | 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers |
| Publisher | Publ by IEEE |
| Pages | 560-563 |
| Number of pages | 4 |
| ISBN (Print) | 0818621575 |
| Publication status | Published - 1992 |
| Externally published | Yes |
| Event | 1991 IEEE International Conference on Computer-Aided Design - ICCAD-91 - Santa Clara, CA, USA Duration: Nov 11 1991 → Nov 14 1991 |
Other
| Other | 1991 IEEE International Conference on Computer-Aided Design - ICCAD-91 |
|---|---|
| City | Santa Clara, CA, USA |
| Period | 11/11/91 → 11/14/91 |
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All Science Journal Classification (ASJC) codes
- Engineering(all)
Cite this
Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs. / Fujita, Masahiro; Matsunaga, Yusuke.
1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers. Publ by IEEE, 1992. p. 560-563.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs
AU - Fujita, Masahiro
AU - Matsunaga, Yusuke
PY - 1992
Y1 - 1992
N2 - The authors present a method for multilevel logic minimization which is particularly suitable for the minimization of look-up table type FPGAs (field programmable gate arrays). Given a set of nodes to be minimized, one first calculates sets of supports which are necessary to construct the functions for the given nodes by applying functional reduction. The functional reduction process guarantees that one can get the minimal support for each node. One then makes a covering table for the set of nodes to be minimized so that one can get the minimal supports to cover all the functions for the given set of nodes to be minimized. The authors present a preliminary implementation and its results for ISCAS combinational benchmark circuits combined with MIS2.1 standard script and a Boolean resubstitution minimizer, and show the effectiveness of the presented method.
AB - The authors present a method for multilevel logic minimization which is particularly suitable for the minimization of look-up table type FPGAs (field programmable gate arrays). Given a set of nodes to be minimized, one first calculates sets of supports which are necessary to construct the functions for the given nodes by applying functional reduction. The functional reduction process guarantees that one can get the minimal support for each node. One then makes a covering table for the set of nodes to be minimized so that one can get the minimal supports to cover all the functions for the given set of nodes to be minimized. The authors present a preliminary implementation and its results for ISCAS combinational benchmark circuits combined with MIS2.1 standard script and a Boolean resubstitution minimizer, and show the effectiveness of the presented method.
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UR - http://www.scopus.com/inward/citedby.url?scp=0027045913&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0027045913
SN - 0818621575
SP - 560
EP - 563
BT - 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers
PB - Publ by IEEE
ER -