Multi-level logic optimization using binary decision diagrams

Yusuke Matsunaga, Masahiro Fujita

Research output: Chapter in Book/Report/Conference proceedingConference contribution

28 Citations (Scopus)

Abstract

A multilevel logic optimizer, which is based on the transduction method, is introduced. The original transduction method is good for optimization, but its calculation time and storage area increase exponentially with the number of inputs because of the use of truth tables. To save CPU time and memory space, the authors implemented this algorithm using ordered binary decision diagrams (OBDD) as the data structure for representing logic functions. Since OBDD does not become as large as other representations, it can handle large circuits without partitioning.

Original languageEnglish
Title of host publicationIEEE Int Conf Comput Aided Des ICCAD 89 Dig Tech Pap
Editors Anon
PublisherPubl by IEEE
Pages556-559
Number of pages4
ISBN (Print)0818659866
Publication statusPublished - 1989
Externally publishedYes
EventIEEE International Conference on Computer-Aided Design (ICCAD-89): Digest of Technical Papers - Santa Clara, CA, USA
Duration: Nov 5 1989Nov 9 1989

Other

OtherIEEE International Conference on Computer-Aided Design (ICCAD-89): Digest of Technical Papers
CitySanta Clara, CA, USA
Period11/5/8911/9/89

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Matsunaga, Y., & Fujita, M. (1989). Multi-level logic optimization using binary decision diagrams. In Anon (Ed.), IEEE Int Conf Comput Aided Des ICCAD 89 Dig Tech Pap (pp. 556-559). Publ by IEEE.