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Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure
S. Yoshimoto, T. Amashita, D. Kozuwa, T. Takata, M. Yoshimura, Y. Matsunaga, H. Yasuura, H. Kawaguchi, M. Yoshimoto
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
11
Citations
(Scopus)