Multiplier energy reduction through bypassing of partial products

Jun Ni Ohban; V. G. Moshnyaga; K. Inoue

doi:10.1109/APCCAS.2002.1115097

Multiplier energy reduction through bypassing of partial products

Jun Ni Ohban, V. G. Moshnyaga, K. Inoue

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

57 Citations (Scopus)

Abstract

The design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. This paper presents a novel approach to reduce power consumption of digital multiplier based on dynamic bypassing of partial products. The bypassing elements incorporated into the multiplier hardware eliminate redundant signal transitions, which appear within the carry-save adders when the partial product is zero. Simulations on the real-life DCT data show that the proposed approach can improve power saving of related methods by 12%, while jointly with them, it reduces the power consumption of a 16x16 digital CMOS multiplier by 31%, with 25% area overhead and less than 4% performance degradation in the worst case. The circuit implementation is outlined.

Original language	English
Title of host publication	Proceedings - APCCAS 2002
Subtitle of host publication	Asia-Pacific Conference on Circuits and Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	13-17
Number of pages	5
ISBN (Electronic)	0780376900
DOIs	https://doi.org/10.1109/APCCAS.2002.1115097
Publication status	Published - Jan 1 2002
Externally published	Yes
Event	Asia-Pacific Conference on Circuits and Systems, APCCAS 2002 - Denpasar, Bali, Indonesia Duration: Oct 28 2002 → Oct 31 2002

Publication series

Name	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
Volume	2

Other

Other	Asia-Pacific Conference on Circuits and Systems, APCCAS 2002
Country	Indonesia
City	Denpasar, Bali
Period	10/28/02 → 10/31/02

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/APCCAS.2002.1115097

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Ohban, J. N., Moshnyaga, V. G., & Inoue, K. (2002). Multiplier energy reduction through bypassing of partial products. In Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems (pp. 13-17). [1115097] (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; Vol. 2). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2002.1115097

Multiplier energy reduction through bypassing of partial products. / Ohban, Jun Ni; Moshnyaga, V. G.; Inoue, K.

Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2002. p. 13-17 1115097 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; Vol. 2).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ohban, JN, Moshnyaga, VG & Inoue, K 2002, Multiplier energy reduction through bypassing of partial products. in Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems., 1115097, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, vol. 2, Institute of Electrical and Electronics Engineers Inc., pp. 13-17, Asia-Pacific Conference on Circuits and Systems, APCCAS 2002, Denpasar, Bali, Indonesia, 10/28/02. https://doi.org/10.1109/APCCAS.2002.1115097

Ohban JN, Moshnyaga VG, Inoue K. Multiplier energy reduction through bypassing of partial products. In Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc. 2002. p. 13-17. 1115097. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2002.1115097

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Multiplier energy reduction through bypassing of partial products

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