Multiplier energy reduction through bypassing of partial products

Jun Ni Ohban, V. G. Moshnyaga, Inoue Koji

Research output: Chapter in Book/Report/Conference proceedingConference contribution

55 Citations (Scopus)

Abstract

The design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. This paper presents a novel approach to reduce power consumption of digital multiplier based on dynamic bypassing of partial products. The bypassing elements incorporated into the multiplier hardware eliminate redundant signal transitions, which appear within the carry-save adders when the partial product is zero. Simulations on the real-life DCT data show that the proposed approach can improve power saving of related methods by 12%, while jointly with them, it reduces the power consumption of a 16x16 digital CMOS multiplier by 31%, with 25% area overhead and less than 4% performance degradation in the worst case. The circuit implementation is outlined.

Original languageEnglish
Title of host publicationProceedings - APCCAS 2002
Subtitle of host publicationAsia-Pacific Conference on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages13-17
Number of pages5
Volume2
ISBN (Electronic)0780376900
DOIs
Publication statusPublished - Jan 1 2002
Externally publishedYes
EventAsia-Pacific Conference on Circuits and Systems, APCCAS 2002 - Denpasar, Bali, Indonesia
Duration: Oct 28 2002Oct 31 2002

Other

OtherAsia-Pacific Conference on Circuits and Systems, APCCAS 2002
CountryIndonesia
CityDenpasar, Bali
Period10/28/0210/31/02

Fingerprint

Electric power utilization
Networks (circuits)
Adders
Hardware
Degradation

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Ohban, J. N., Moshnyaga, V. G., & Koji, I. (2002). Multiplier energy reduction through bypassing of partial products. In Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems (Vol. 2, pp. 13-17). [1115097] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2002.1115097

Multiplier energy reduction through bypassing of partial products. / Ohban, Jun Ni; Moshnyaga, V. G.; Koji, Inoue.

Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems. Vol. 2 Institute of Electrical and Electronics Engineers Inc., 2002. p. 13-17 1115097.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ohban, JN, Moshnyaga, VG & Koji, I 2002, Multiplier energy reduction through bypassing of partial products. in Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems. vol. 2, 1115097, Institute of Electrical and Electronics Engineers Inc., pp. 13-17, Asia-Pacific Conference on Circuits and Systems, APCCAS 2002, Denpasar, Bali, Indonesia, 10/28/02. https://doi.org/10.1109/APCCAS.2002.1115097
Ohban JN, Moshnyaga VG, Koji I. Multiplier energy reduction through bypassing of partial products. In Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems. Vol. 2. Institute of Electrical and Electronics Engineers Inc. 2002. p. 13-17. 1115097 https://doi.org/10.1109/APCCAS.2002.1115097
Ohban, Jun Ni ; Moshnyaga, V. G. ; Koji, Inoue. / Multiplier energy reduction through bypassing of partial products. Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems. Vol. 2 Institute of Electrical and Electronics Engineers Inc., 2002. pp. 13-17
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