Abstract
A new methodology to evaluate the process temperature dependence of the minority carrier lifetime has been developed. A TEG layout with p+-stripes on an n-Si substrate was designed. When all the p+n junctions are made forward, the minority carrier diffusion current flows one dimensionally into the substrate. On the other hand, for making only the one center p+n junction forward, the current spreads laterally and flows cylindrically into the substrate. By the difference in the flow path of the minority carrier diffusion, we can successfully extract the minority carrier lifetime. We applied this methodology to the evaluation of the minority carrier lifetime depending on process temperatures and confirmed the lifetime degradation for high temperature process.
| Original language | English |
|---|---|
| Title of host publication | 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 105-106 |
| Number of pages | 2 |
| ISBN (Electronic) | 9781538667002 |
| DOIs | |
| Publication status | Published - Oct 22 2018 |
| Event | 32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 - Honolulu, United States Duration: Jun 18 2018 → Jun 22 2018 |
Publication series
| Name | IEEE Symposium on VLSI Circuits, Digest of Technical Papers |
|---|---|
| Volume | 2018-June |
Other
| Other | 32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 |
|---|---|
| Country | United States |
| City | Honolulu |
| Period | 6/18/18 → 6/22/18 |
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All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
Cite this
New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment. / Kakushima, K.; Hoshii, T.; Watanabe, M.; Shizyo, N.; Furukawa, K.; Saraya, T.; Takakura, T.; Itou, K.; Fukui, M.; Suzuki, S.; Takeuchi, K.; Muneta, I.; Wakabayashi, H.; Numasawa, Y.; Ogura, A.; Nishizawa, Shinichi; Tsutsui, K.; Hiramoto, T.; Ohashi, H.; Iwai, H.
2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 105-106 8502399 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2018-June).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment
AU - Kakushima, K.
AU - Hoshii, T.
AU - Watanabe, M.
AU - Shizyo, N.
AU - Furukawa, K.
AU - Saraya, T.
AU - Takakura, T.
AU - Itou, K.
AU - Fukui, M.
AU - Suzuki, S.
AU - Takeuchi, K.
AU - Muneta, I.
AU - Wakabayashi, H.
AU - Numasawa, Y.
AU - Ogura, A.
AU - Nishizawa, Shinichi
AU - Tsutsui, K.
AU - Hiramoto, T.
AU - Ohashi, H.
AU - Iwai, H.
PY - 2018/10/22
Y1 - 2018/10/22
N2 - A new methodology to evaluate the process temperature dependence of the minority carrier lifetime has been developed. A TEG layout with p+-stripes on an n-Si substrate was designed. When all the p+n junctions are made forward, the minority carrier diffusion current flows one dimensionally into the substrate. On the other hand, for making only the one center p+n junction forward, the current spreads laterally and flows cylindrically into the substrate. By the difference in the flow path of the minority carrier diffusion, we can successfully extract the minority carrier lifetime. We applied this methodology to the evaluation of the minority carrier lifetime depending on process temperatures and confirmed the lifetime degradation for high temperature process.
AB - A new methodology to evaluate the process temperature dependence of the minority carrier lifetime has been developed. A TEG layout with p+-stripes on an n-Si substrate was designed. When all the p+n junctions are made forward, the minority carrier diffusion current flows one dimensionally into the substrate. On the other hand, for making only the one center p+n junction forward, the current spreads laterally and flows cylindrically into the substrate. By the difference in the flow path of the minority carrier diffusion, we can successfully extract the minority carrier lifetime. We applied this methodology to the evaluation of the minority carrier lifetime depending on process temperatures and confirmed the lifetime degradation for high temperature process.
UR - http://www.scopus.com/inward/record.url?scp=85056870621&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85056870621&partnerID=8YFLogxK
U2 - 10.1109/VLSIC.2018.8502399
DO - 10.1109/VLSIC.2018.8502399
M3 - Conference contribution
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - 105
EP - 106
BT - 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
PB - Institute of Electrical and Electronics Engineers Inc.
ER -