New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment

K. Kakushima; T. Hoshii; M. Watanabe; N. Shizyo; K. Furukawa; T. Saraya; T. Takakura; K. Itou; M. Fukui; S. Suzuki; K. Takeuchi; I. Muneta; H. Wakabayashi; Y. Numasawa; A. Ogura; S. Nishizawa; K. Tsutsui; T. Hiramoto; H. Ohashi; H. Iwai

doi:10.1109/VLSIC.2018.8502399

New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment

K. Kakushima, T. Hoshii, M. Watanabe, N. Shizyo, K. Furukawa, T. Saraya, T. Takakura, K. Itou, M. Fukui, S. Suzuki, K. Takeuchi, I. Muneta, H. Wakabayashi, Y. Numasawa, A. Ogura, S. Nishizawa, K. Tsutsui, T. Hiramoto, H. Ohashi, H. Iwai

Renewable Energy Center

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

A new methodology to evaluate the process temperature dependence of the minority carrier lifetime has been developed. A TEG layout with p+-stripes on an n-Si substrate was designed. When all the p+n junctions are made forward, the minority carrier diffusion current flows one dimensionally into the substrate. On the other hand, for making only the one center p+n junction forward, the current spreads laterally and flows cylindrically into the substrate. By the difference in the flow path of the minority carrier diffusion, we can successfully extract the minority carrier lifetime. We applied this methodology to the evaluation of the minority carrier lifetime depending on process temperatures and confirmed the lifetime degradation for high temperature process.

Original language	English
Title of host publication	2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	105-106
Number of pages	2
ISBN (Electronic)	9781538667002
DOIs	https://doi.org/10.1109/VLSIC.2018.8502399
Publication status	Published - Oct 22 2018
Event	32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 - Honolulu, United States Duration: Jun 18 2018 → Jun 22 2018

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2018-June

Other

Other	32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
Country/Territory	United States
City	Honolulu
Period	6/18/18 → 6/22/18

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/VLSIC.2018.8502399

Cite this

Kakushima, K., Hoshii, T., Watanabe, M., Shizyo, N., Furukawa, K., Saraya, T., Takakura, T., Itou, K., Fukui, M., Suzuki, S., Takeuchi, K., Muneta, I., Wakabayashi, H., Numasawa, Y., Ogura, A., Nishizawa, S., Tsutsui, K., Hiramoto, T., Ohashi, H., & Iwai, H. (2018). New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment. In 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 (pp. 105-106). [8502399] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2018-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2018.8502399

New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment. / Kakushima, K.; Hoshii, T.; Watanabe, M.; Shizyo, N.; Furukawa, K.; Saraya, T.; Takakura, T.; Itou, K.; Fukui, M.; Suzuki, S.; Takeuchi, K.; Muneta, I.; Wakabayashi, H.; Numasawa, Y.; Ogura, A.; Nishizawa, S.; Tsutsui, K.; Hiramoto, T.; Ohashi, H.; Iwai, H.

2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 105-106 8502399 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2018-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kakushima, K, Hoshii, T, Watanabe, M, Shizyo, N, Furukawa, K, Saraya, T, Takakura, T, Itou, K, Fukui, M, Suzuki, S, Takeuchi, K, Muneta, I, Wakabayashi, H, Numasawa, Y, Ogura, A, Nishizawa, S, Tsutsui, K, Hiramoto, T, Ohashi, H & Iwai, H 2018, New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment. in 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018., 8502399, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2018-June, Institute of Electrical and Electronics Engineers Inc., pp. 105-106, 32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018, Honolulu, United States, 6/18/18. https://doi.org/10.1109/VLSIC.2018.8502399

Kakushima K, Hoshii T, Watanabe M, Shizyo N, Furukawa K, Saraya T et al. New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment. In 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 105-106. 8502399. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2018.8502399

Kakushima, K. ; Hoshii, T. ; Watanabe, M. ; Shizyo, N. ; Furukawa, K. ; Saraya, T. ; Takakura, T. ; Itou, K. ; Fukui, M. ; Suzuki, S. ; Takeuchi, K. ; Muneta, I. ; Wakabayashi, H. ; Numasawa, Y. ; Ogura, A. ; Nishizawa, S. ; Tsutsui, K. ; Hiramoto, T. ; Ohashi, H. ; Iwai, H. / New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment. 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 105-106 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

@inproceedings{2ad7e9da3f694277950b1ec51cc4d69d,

title = "New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment",

abstract = "A new methodology to evaluate the process temperature dependence of the minority carrier lifetime has been developed. A TEG layout with p+-stripes on an n-Si substrate was designed. When all the p+n junctions are made forward, the minority carrier diffusion current flows one dimensionally into the substrate. On the other hand, for making only the one center p+n junction forward, the current spreads laterally and flows cylindrically into the substrate. By the difference in the flow path of the minority carrier diffusion, we can successfully extract the minority carrier lifetime. We applied this methodology to the evaluation of the minority carrier lifetime depending on process temperatures and confirmed the lifetime degradation for high temperature process.",

author = "K. Kakushima and T. Hoshii and M. Watanabe and N. Shizyo and K. Furukawa and T. Saraya and T. Takakura and K. Itou and M. Fukui and S. Suzuki and K. Takeuchi and I. Muneta and H. Wakabayashi and Y. Numasawa and A. Ogura and S. Nishizawa and K. Tsutsui and T. Hiramoto and H. Ohashi and H. Iwai",

note = "Funding Information: The authors would like to thank K. Sato of Mitsubishi Electric Co., T. Matsudai and W. Saito of Toshiba Electronic Devices & Storage Corp. for fruitful discussions. This work is based on results obtained from a project commissioned by New Energy and Industrial Technology Development Organization (NEDO). Publisher Copyright: {\textcopyright} 2018 IEEE.; 32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 ; Conference date: 18-06-2018 Through 22-06-2018",

year = "2018",

month = oct,

day = "22",

doi = "10.1109/VLSIC.2018.8502399",

language = "English",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "105--106",

booktitle = "2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018",

address = "United States",

}

TY - GEN

T1 - New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment

AU - Kakushima, K.

AU - Hoshii, T.

AU - Watanabe, M.

AU - Shizyo, N.

AU - Furukawa, K.

AU - Saraya, T.

AU - Takakura, T.

AU - Itou, K.

AU - Fukui, M.

AU - Suzuki, S.

AU - Takeuchi, K.

AU - Muneta, I.

AU - Wakabayashi, H.

AU - Numasawa, Y.

AU - Ogura, A.

AU - Nishizawa, S.

AU - Tsutsui, K.

AU - Hiramoto, T.

AU - Ohashi, H.

AU - Iwai, H.

N1 - Funding Information: The authors would like to thank K. Sato of Mitsubishi Electric Co., T. Matsudai and W. Saito of Toshiba Electronic Devices & Storage Corp. for fruitful discussions. This work is based on results obtained from a project commissioned by New Energy and Industrial Technology Development Organization (NEDO). Publisher Copyright: © 2018 IEEE.

PY - 2018/10/22

Y1 - 2018/10/22

N2 - A new methodology to evaluate the process temperature dependence of the minority carrier lifetime has been developed. A TEG layout with p+-stripes on an n-Si substrate was designed. When all the p+n junctions are made forward, the minority carrier diffusion current flows one dimensionally into the substrate. On the other hand, for making only the one center p+n junction forward, the current spreads laterally and flows cylindrically into the substrate. By the difference in the flow path of the minority carrier diffusion, we can successfully extract the minority carrier lifetime. We applied this methodology to the evaluation of the minority carrier lifetime depending on process temperatures and confirmed the lifetime degradation for high temperature process.

AB - A new methodology to evaluate the process temperature dependence of the minority carrier lifetime has been developed. A TEG layout with p+-stripes on an n-Si substrate was designed. When all the p+n junctions are made forward, the minority carrier diffusion current flows one dimensionally into the substrate. On the other hand, for making only the one center p+n junction forward, the current spreads laterally and flows cylindrically into the substrate. By the difference in the flow path of the minority carrier diffusion, we can successfully extract the minority carrier lifetime. We applied this methodology to the evaluation of the minority carrier lifetime depending on process temperatures and confirmed the lifetime degradation for high temperature process.

UR - http://www.scopus.com/inward/record.url?scp=85056870621&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85056870621&partnerID=8YFLogxK

U2 - 10.1109/VLSIC.2018.8502399

DO - 10.1109/VLSIC.2018.8502399

M3 - Conference contribution

AN - SCOPUS:85056870621

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - 105

EP - 106

BT - 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018

Y2 - 18 June 2018 through 22 June 2018

ER -

New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment

Abstract

Publication series

Other

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this