Novel test methodology for core-based system LSIs and a testing time minimization problem

Makoto Sugihara; Hiroshi Date; Hiroto Yasuura

doi:10.1109/TEST.1998.743187

Novel test methodology for core-based system LSIs and a testing time minimization problem

Makoto Sugihara, Hiroshi Date, Hiroto Yasuura

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

50 Citations (Scopus)

Abstract

In this paper, we propose a novel test methodology for core-based system LSIs. Our test methodology aims to decrease testing time for core-based system LSIs. Considering testing time reduction, our test methodology is based on BIST and ATPG. The main contributions of this paper are summarized as follows. (i). BIST is efficiently combined with external testing to relax the limitation of the external primary inputs and outputs. (ii). External testing for one of cores and BISTs for the others are performed in parallel to reduce the total testing time. (iii). The testing time minimization problem for core-based system LSIs is formulated as a combinatorial optimization problem to select the optimal set of test vectors from given sets of test vectors for each core.

Original language	English
Title of host publication	IEEE International Test Conference (TC)
Editors	Anon
Pages	465-472
Number of pages	8
DOIs	https://doi.org/10.1109/TEST.1998.743187
Publication status	Published - Dec 1 1998
Event	Proceedings of the 1998 IEEE International Test Conference - Washington, DC, USA Duration: Oct 18 1998 → Oct 21 1998

Publication series

Name	IEEE International Test Conference (TC)
ISSN (Print)	1089-3539

Other

Other	Proceedings of the 1998 IEEE International Test Conference
City	Washington, DC, USA
Period	10/18/98 → 10/21/98

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Applied Mathematics

Access to Document

10.1109/TEST.1998.743187

Cite this

Sugihara, M, Date, H & Yasuura, H 1998, Novel test methodology for core-based system LSIs and a testing time minimization problem. in Anon (ed.), IEEE International Test Conference (TC). IEEE International Test Conference (TC), pp. 465-472, Proceedings of the 1998 IEEE International Test Conference, Washington, DC, USA, 10/18/98. https://doi.org/10.1109/TEST.1998.743187

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title = "Novel test methodology for core-based system LSIs and a testing time minimization problem",

abstract = "In this paper, we propose a novel test methodology for core-based system LSIs. Our test methodology aims to decrease testing time for core-based system LSIs. Considering testing time reduction, our test methodology is based on BIST and ATPG. The main contributions of this paper are summarized as follows. (i). BIST is efficiently combined with external testing to relax the limitation of the external primary inputs and outputs. (ii). External testing for one of cores and BISTs for the others are performed in parallel to reduce the total testing time. (iii). The testing time minimization problem for core-based system LSIs is formulated as a combinatorial optimization problem to select the optimal set of test vectors from given sets of test vectors for each core.",

author = "Makoto Sugihara and Hiroshi Date and Hiroto Yasuura",

year = "1998",

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doi = "10.1109/TEST.1998.743187",

language = "English",

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series = "IEEE International Test Conference (TC)",

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AU - Sugihara, Makoto

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AU - Yasuura, Hiroto

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N2 - In this paper, we propose a novel test methodology for core-based system LSIs. Our test methodology aims to decrease testing time for core-based system LSIs. Considering testing time reduction, our test methodology is based on BIST and ATPG. The main contributions of this paper are summarized as follows. (i). BIST is efficiently combined with external testing to relax the limitation of the external primary inputs and outputs. (ii). External testing for one of cores and BISTs for the others are performed in parallel to reduce the total testing time. (iii). The testing time minimization problem for core-based system LSIs is formulated as a combinatorial optimization problem to select the optimal set of test vectors from given sets of test vectors for each core.

AB - In this paper, we propose a novel test methodology for core-based system LSIs. Our test methodology aims to decrease testing time for core-based system LSIs. Considering testing time reduction, our test methodology is based on BIST and ATPG. The main contributions of this paper are summarized as follows. (i). BIST is efficiently combined with external testing to relax the limitation of the external primary inputs and outputs. (ii). External testing for one of cores and BISTs for the others are performed in parallel to reduce the total testing time. (iii). The testing time minimization problem for core-based system LSIs is formulated as a combinatorial optimization problem to select the optimal set of test vectors from given sets of test vectors for each core.

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Novel test methodology for core-based system LSIs and a testing time minimization problem

Abstract

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