Novel test methodology for core-based system LSIs and a testing time minimization problem

Makoto Sugihara, Hiroshi Date, Hiroto Yasuura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

49 Citations (Scopus)

Abstract

In this paper, we propose a novel test methodology for core-based system LSIs. Our test methodology aims to decrease testing time for core-based system LSIs. Considering testing time reduction, our test methodology is based on BIST and ATPG. The main contributions of this paper are summarized as follows. (i). BIST is efficiently combined with external testing to relax the limitation of the external primary inputs and outputs. (ii). External testing for one of cores and BISTs for the others are performed in parallel to reduce the total testing time. (iii). The testing time minimization problem for core-based system LSIs is formulated as a combinatorial optimization problem to select the optimal set of test vectors from given sets of test vectors for each core.

Original languageEnglish
Title of host publicationIEEE International Test Conference (TC)
Editors Anon
Pages465-472
Number of pages8
DOIs
Publication statusPublished - Dec 1 1998
EventProceedings of the 1998 IEEE International Test Conference - Washington, DC, USA
Duration: Oct 18 1998Oct 21 1998

Publication series

NameIEEE International Test Conference (TC)
ISSN (Print)1089-3539

Other

OtherProceedings of the 1998 IEEE International Test Conference
CityWashington, DC, USA
Period10/18/9810/21/98

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics

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  • Cite this

    Sugihara, M., Date, H., & Yasuura, H. (1998). Novel test methodology for core-based system LSIs and a testing time minimization problem. In Anon (Ed.), IEEE International Test Conference (TC) (pp. 465-472). (IEEE International Test Conference (TC)). https://doi.org/10.1109/TEST.1998.743187