N+Si/pGe heterojunctions fabricated by low temperature ribbon bonding with passivating interlayer

Tony Chi Liu; Shoichi Kabuyanagi; Tomonori Nishimura; Takeaki Yajima; Akira Toriumi

doi:10.1109/LED.2017.2699658

N+Si/pGe heterojunctions fabricated by low temperature ribbon bonding with passivating interlayer

Tony Chi Liu, Shoichi Kabuyanagi, Tomonori Nishimura, Takeaki Yajima, Akira Toriumi

Research output: Contribution to journal › Article › peer-review

5 Citations (Scopus)

Abstract

A bonding technique via passivating interlayer formation is proposed for bulkmaterial heterojunction fabrication. n+Si/pGe heterojunctions were fabricated by a ribbon bonding with interfaces passivated by an amorphous interlayer. With a highest process temperature as low as 150 °C, the bonded junctions exhibited rectifying characteristics with a turn-on voltage of 0.3 V as an ideal Si/Ge heterojunction and an ideality factor of 2.15. This technique shows a great potential for bulk material heterojunction formation, especially when ultimately abrupt junctions and low temperature processes are needed.

Original language	English
Article number	7914753
Pages (from-to)	716-719
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	38
Issue number	6
DOIs	https://doi.org/10.1109/LED.2017.2699658
Publication status	Published - Jun 2017
Externally published	Yes

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/LED.2017.2699658

Fingerprint Dive into the research topics of 'N+Si/pGe heterojunctions fabricated by low temperature ribbon bonding with passivating interlayer'. Together they form a unique fingerprint.

Cite this

@article{53780313e33048809ebb80cf1d588ec0,

title = "N+Si/pGe heterojunctions fabricated by low temperature ribbon bonding with passivating interlayer",

abstract = "A bonding technique via passivating interlayer formation is proposed for bulkmaterial heterojunction fabrication. n+Si/pGe heterojunctions were fabricated by a ribbon bonding with interfaces passivated by an amorphous interlayer. With a highest process temperature as low as 150 °C, the bonded junctions exhibited rectifying characteristics with a turn-on voltage of 0.3 V as an ideal Si/Ge heterojunction and an ideality factor of 2.15. This technique shows a great potential for bulk material heterojunction formation, especially when ultimately abrupt junctions and low temperature processes are needed.",

author = "Liu, {Tony Chi} and Shoichi Kabuyanagi and Tomonori Nishimura and Takeaki Yajima and Akira Toriumi",

year = "2017",

month = jun,

doi = "10.1109/LED.2017.2699658",

language = "English",

volume = "38",

pages = "716--719",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "6",

}

TY - JOUR

T1 - N+Si/pGe heterojunctions fabricated by low temperature ribbon bonding with passivating interlayer

AU - Liu, Tony Chi

AU - Kabuyanagi, Shoichi

AU - Nishimura, Tomonori

AU - Yajima, Takeaki

AU - Toriumi, Akira

PY - 2017/6

Y1 - 2017/6

N2 - A bonding technique via passivating interlayer formation is proposed for bulkmaterial heterojunction fabrication. n+Si/pGe heterojunctions were fabricated by a ribbon bonding with interfaces passivated by an amorphous interlayer. With a highest process temperature as low as 150 °C, the bonded junctions exhibited rectifying characteristics with a turn-on voltage of 0.3 V as an ideal Si/Ge heterojunction and an ideality factor of 2.15. This technique shows a great potential for bulk material heterojunction formation, especially when ultimately abrupt junctions and low temperature processes are needed.

AB - A bonding technique via passivating interlayer formation is proposed for bulkmaterial heterojunction fabrication. n+Si/pGe heterojunctions were fabricated by a ribbon bonding with interfaces passivated by an amorphous interlayer. With a highest process temperature as low as 150 °C, the bonded junctions exhibited rectifying characteristics with a turn-on voltage of 0.3 V as an ideal Si/Ge heterojunction and an ideality factor of 2.15. This technique shows a great potential for bulk material heterojunction formation, especially when ultimately abrupt junctions and low temperature processes are needed.

UR - http://www.scopus.com/inward/record.url?scp=85021751400&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85021751400&partnerID=8YFLogxK

U2 - 10.1109/LED.2017.2699658

DO - 10.1109/LED.2017.2699658

M3 - Article

AN - SCOPUS:85021751400

VL - 38

SP - 716

EP - 719

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

SN - 0741-3106

IS - 6

M1 - 7914753

ER -