In this paper, we propose a novel architecture for low-power direct-mapped instruction caches, called "history-based tag-comparison (HBTC) cache". The cache attempts to reuse tag-comparison results for avoiding unnecessary tag checks. Execution footprints are recorded into an extended BTB (Branch Target Buffer). In our evaluation, it is observed that the energy for tag comparison can be reduced by more than 90% in many applications.
|Number of pages||9|
|Journal||IEICE Transactions on Electronics|
|Publication status||Published - Feb 2002|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering