Omitting cache look-up for high-performance, low-power microprocessors

Inoue Koji, Vasily G. Moshnyaga, Kazuaki Murakami

Research output: Contribution to journalArticle

Abstract

In this paper, we propose a novel architecture for low-power direct-mapped instruction caches, called "history-based tag-comparison (HBTC) cache". The cache attempts to reuse tag-comparison results for avoiding unnecessary tag checks. Execution footprints are recorded into an extended BTB (Branch Target Buffer). In our evaluation, it is observed that the energy for tag comparison can be reduced by more than 90% in many applications.

Original languageEnglish
Pages (from-to)279-287
Number of pages9
JournalIEICE Transactions on Electronics
VolumeE85-C
Issue number2
Publication statusPublished - Feb 2002
Externally publishedYes

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Microprocessor chips
Buffers

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Omitting cache look-up for high-performance, low-power microprocessors. / Koji, Inoue; Moshnyaga, Vasily G.; Murakami, Kazuaki.

In: IEICE Transactions on Electronics, Vol. E85-C, No. 2, 02.2002, p. 279-287.

Research output: Contribution to journalArticle

Koji, Inoue ; Moshnyaga, Vasily G. ; Murakami, Kazuaki. / Omitting cache look-up for high-performance, low-power microprocessors. In: IEICE Transactions on Electronics. 2002 ; Vol. E85-C, No. 2. pp. 279-287.
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