In this paper, an improved design of a SAT-solver PCMGTP on FPGA is described. The previous implementation of PCMGTP achieved considerable speedup of SAT-solving compared to the software counterpart of MGTP. After intensive analyses and experiments, it turned out that the early design contains much redundancy and has room for improvement. Also, we developed a generic description style in Verilog using arrays and iterative constructs. Experimental results show that the new implementation outperforms the old one with regard to both execution time and circuit size.
|Number of pages||6|
|Journal||Research Reports on Information Science and Electrical Engineering of Kyushu University|
|Publication status||Published - Mar 1 2005|
All Science Journal Classification (ASJC) codes
- Computer Science(all)
- Electrical and Electronic Engineering