On variable ordering of binary decision diagrams for the application of multi-level logic synthesis

Masahiro Fujita, Yusuke Matsunaga, Taeko Kakuda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

97 Citations (Scopus)

Abstract

We have developed multi-level logic minimization programs using Binary Decision Diagram (BDD). Here we present variable ordering methods of BDD. The variable ordering algorithm for two-level circuits is based on cover patterns and selects most binate variables first, and the one for multi-level circuits is based on depth first traverse of circuits. In both cases, the acquired variable orderings are optimized by exchanging a variable with its neighbor in the ordering.

Original languageEnglish
Title of host publicationProc Eur Conf Des Autom
PublisherPubl by IEEE
Pages50-54
Number of pages5
ISBN (Print)0818626453
Publication statusPublished - Dec 1 1992
Externally publishedYes
EventProceedings the European Conference on Design Automation - Amsterdam, Neth
Duration: Mar 16 1992Mar 19 1992

Publication series

NameProc Eur Conf Des Autom

Other

OtherProceedings the European Conference on Design Automation
CityAmsterdam, Neth
Period3/16/923/19/92

Fingerprint

Binary decision diagrams
Networks (circuits)
Logic Synthesis

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Fujita, M., Matsunaga, Y., & Kakuda, T. (1992). On variable ordering of binary decision diagrams for the application of multi-level logic synthesis. In Proc Eur Conf Des Autom (pp. 50-54). (Proc Eur Conf Des Autom). Publ by IEEE.

On variable ordering of binary decision diagrams for the application of multi-level logic synthesis. / Fujita, Masahiro; Matsunaga, Yusuke; Kakuda, Taeko.

Proc Eur Conf Des Autom. Publ by IEEE, 1992. p. 50-54 (Proc Eur Conf Des Autom).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fujita, M, Matsunaga, Y & Kakuda, T 1992, On variable ordering of binary decision diagrams for the application of multi-level logic synthesis. in Proc Eur Conf Des Autom. Proc Eur Conf Des Autom, Publ by IEEE, pp. 50-54, Proceedings the European Conference on Design Automation, Amsterdam, Neth, 3/16/92.
Fujita M, Matsunaga Y, Kakuda T. On variable ordering of binary decision diagrams for the application of multi-level logic synthesis. In Proc Eur Conf Des Autom. Publ by IEEE. 1992. p. 50-54. (Proc Eur Conf Des Autom).
Fujita, Masahiro ; Matsunaga, Yusuke ; Kakuda, Taeko. / On variable ordering of binary decision diagrams for the application of multi-level logic synthesis. Proc Eur Conf Des Autom. Publ by IEEE, 1992. pp. 50-54 (Proc Eur Conf Des Autom).
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