Parallel exhaustive search for several np-complete problems using content addressable memories

Hiroto Yasuura, Taizo Tsujimoto, Keikichi Tamaru

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The authors propose a simple parallel algorithm design technique for several NP-complete problems called parallel exhaustive search. Algorithms can be implemented on an SIMD (single instruction, multiple data flow) architecture with very simple and regular array structure. Actually, the architecture is realized by a content-addressable memory (CAM). The authors design almost-linear algorithms for several NP-complete problems by this approach and estimate the performance and limitation. The computation time of the parallel algorithm for the knapsack problem using the CAM is evaluated, and it is shown that the parallel algorithm is 100 or 1000 times faster than the sequential algorithms.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherPubl by IEEE
Pages333-336
Number of pages4
ISBN (Print)9517212399
Publication statusPublished - Dec 1 1988
Externally publishedYes

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume1
ISSN (Print)0271-4310

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All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Yasuura, H., Tsujimoto, T., & Tamaru, K. (1988). Parallel exhaustive search for several np-complete problems using content addressable memories. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 333-336). (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 1). Publ by IEEE.