To satisfy the ever-increasing requirement from load-side and improve the power quality, the paralleled converters structure is seen to be an interesting solution for such purpose. However, paralleled converters suffer from a major challenge related to the excessive circulating currents due to the difference in the induced CMV in each converter. This voltage difference is due to the instantaneous potential difference between paralleled phase-legs. Consequently, ZSCC as well as DMCC shall appear between the paralleled converters. In this context, this paper utilizes the interleaved PWM concept for the ZSCC and DMCC reduction in paralleled SSIs, where this SSI is a single-stage dc-ac converter and the prior mentioned operation and associated issues have never been investigated yet. This paper describes the three-phase SSI structure and its basic operation, and shows the corresponding CMV waveform. Then, based on the shown analysis, an interleaved DPWM strategy is proposed to restrain the CMV amplitude and reduce the induced circulating currents. Furthermore, the effect of changing the modulation index and interleaving angle on the overall converter behavior has also been evaluated in case of using SSI. The analysis and simulations revealed the effectiveness of the proposed modulation strategy compared to counterparts. Finally, the shown simulation results are validated experimentally.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering