Parallelism control scheme in a dataflow architecture

Shigeru Kusakabe, Takahide Hoshide, Rin-Ichiro Taniguchi, Makoto Amamiya

Research output: Chapter in Book/Report/Conference proceedingConference contribution


We propose execution control scheme to realize an efficient multi-processing environment in dataflow architecture. With a unified software and hardware mechanism, we can detect states of processes at run time, which are treated as control information. We control the process level parallelism according to the hardware capacity, and virtualize high speed memory in dynamic data-driven computation where context changes in every instruction execution. We apply this scheme to the Datarol architecture, an optimized version of dynamic dataflow architecture, and evaluate them through software simulation.

Original languageEnglish
Title of host publicationParallel Processing
Subtitle of host publicationCONPAR 1992 ─ VAPP V - 2nd Joint International Conference on Vector and Parallel Processing, Proceedings
EditorsLuc Bouge, Michel Cosnard, Yves Robert, Denis Trystram
PublisherSpringer Verlag
Number of pages6
ISBN (Print)9783540558958
Publication statusPublished - Jan 1 1992
Event2nd Joint International Conference on Vector and Parallel Processing, CONPAR 1992 - Lyon, France
Duration: Sept 1 1992Sept 4 1992

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume634 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


Other2nd Joint International Conference on Vector and Parallel Processing, CONPAR 1992

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Computer Science(all)


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