Performance balancing: Software-based on-chip memory management for effective CMP executions

Naoto Fukumoto, Kenichi Imazato, Inoue Koji, Kazuaki Murakami

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper proposes the concept of performance balancing, and reports its performance impact on a Chip multiprocessor (CMP). Integrating multiple processor cores into a single chip, or CMPs, can achieve higher peak performance by means of exploiting thread level parallelism. However, the off-chip memory bandwidth which does not scale with the number of cores tends to limit the potential of CMPs. To solve this issue, the technique proposed in this paper attempts to make a good balance between computation and memorization. Unlike conventional parallel executions, this approach exploits some cores to improve the memory performance. These cores devote the on-chip memory hardware resources to the remaining cores executing the parallelized threads. In our evaluation, it is observed that our approach can achieve 31% of performance improvement compared to a conventional parallel execution model in the specified program.

Original languageEnglish
Title of host publicationProceedings of the 10th MEDEA Workshop on MEmory Performance
Subtitle of host publicationDEaling with Applications, Systems and Architecture, MEDEA '09, held in conjunction with the PACT 2009 Conference
Pages28-34
Number of pages7
DOIs
Publication statusPublished - Dec 1 2009
Event10th MEDEA Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '09, held in conjunction with the Int. Conf. on Parallel Architectures and Compilation Techniques, PACT 2009 - Raleigh, NC, United States
Duration: Sep 13 2009Sep 13 2009

Publication series

NameACM International Conference Proceeding Series

Other

Other10th MEDEA Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '09, held in conjunction with the Int. Conf. on Parallel Architectures and Compilation Techniques, PACT 2009
CountryUnited States
CityRaleigh, NC
Period9/13/099/13/09

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All Science Journal Classification (ASJC) codes

  • Software
  • Human-Computer Interaction
  • Computer Vision and Pattern Recognition
  • Computer Networks and Communications

Cite this

Fukumoto, N., Imazato, K., Koji, I., & Murakami, K. (2009). Performance balancing: Software-based on-chip memory management for effective CMP executions. In Proceedings of the 10th MEDEA Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '09, held in conjunction with the PACT 2009 Conference (pp. 28-34). (ACM International Conference Proceeding Series). https://doi.org/10.1145/1621960.1621966