Performance enhancement of partially- And fully-depleted strained-SOI MOSFETs and characterization of strained-Si device parameters

Toshinori Numata, Toshifumi Irisawa, Tsutomu Tezuka, Junji Koga, Norio Hirashita, Koji Usuda, Eiji Toyoda, Yosiji Miyamura, Akihito Tanabe, Naoharu Sugiyama, Shin Ichi Takagi

Research output: Contribution to journalConference articlepeer-review

Abstract

This paper demonstrates the successful fabrication of strained-SOI MOSFETs using SiGe on Insulator (SGOI) substrates. 200mm SGOI wafer with Ge content of 30% is fabricated by Ge condensation technique. The performance enhancement over 14% is obtained in gate length of 70 nm. Furthermore, fully-depleted strained-SOI MOSFETs with back gate is demonstrated. Thin strained-Si layer can suppress the abnormal off leakage current due to the enhancement impurity diffusion.

Original languageEnglish
Pages (from-to)177-180
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting, IEDM
Publication statusPublished - 2004
Externally publishedYes
EventIEEE International Electron Devices Meeting, 2004 IEDM - San Francisco, CA, United States
Duration: Dec 13 2004Dec 15 2004

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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