Performance evaluation of 3D stacked multi-core processors with temperature consideration

Takaaki Hanada, Hiroshi Sasaki, Koji Inoue, Kazuaki Murakami

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

3D stacked multi-core processor is one of the applications of 3D integration technology. It achieves high bandwidth access to last level cache and allows to increase the number of cores while maintaining the package area. Although, 3D multi-core temperature increases with the number of stacked dies because of the escalating power density and thermal resistivity. Therefore, 3D multi-cores require lower clock frequencies for keeping the temperature under a safe constraint, so that performance is not always improved. In this paper, we evaluate the performance of 3D stacked multi-cores running under temperature constraints, and we show that there is a trade-off between clock frequency and parallel capability.

Original languageEnglish
Title of host publication2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
DOIs
Publication statusPublished - Dec 1 2011
Event2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 - Osaka, Japan
Duration: Jan 31 2012Feb 2 2012

Publication series

Name2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

Other

Other2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
CountryJapan
CityOsaka
Period1/31/122/2/12

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All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering

Cite this

Hanada, T., Sasaki, H., Inoue, K., & Murakami, K. (2011). Performance evaluation of 3D stacked multi-core processors with temperature consideration. In 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 [6263025] (2011 IEEE International 3D Systems Integration Conference, 3DIC 2011). https://doi.org/10.1109/3DIC.2012.6263025