Performance optimization of SpMV using CRS format by considering OpenMP scheduling on CPUs and MIC

Satoshi Ohshima, Takahiro Katagiri, Masaharu Matsumoto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

In this study, we evaluate the performance of sparse matrix-vector multiplication (SpMV) using the compressed row storage (CRS) format on CPUs and MIC. We focus on the relationship between OpenMP scheduling and performance. The performance of SpMV is measured using various OpenMP scheduling settings and the results are analyzed, which show that OpenMP scheduling has a considerable effect on the performance of SpMV. We confirm that some scheduling settings resulted in performance improvements compared with default scheduling for particular matrices. The results of the evaluation show that the performance of SpMV is improved by up to 1.57 times compared with SPARC64 IXfx, 2.47 times compared with Xeon Ivy Bridge-EP, and 2.26 times compared with Knights Corner. Next, we modify the SpMV function of OpenATLib, an auto-tuned numerical library, to consider the scheduling of optimization as an additional SpMV implementation. We measure the performance of the GMRES solver and obtain performance improvements of up to 11.4%. These results will help to improve the performance of various numerical calculation applications.

Original languageEnglish
Title of host publicationProceedings - 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages253-260
Number of pages8
ISBN (Electronic)9781479943050
DOIs
Publication statusPublished - Nov 6 2014
Externally publishedYes
Event2014 8th IEEE International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014 - Aizu-Wakamatsu, Japan
Duration: Sept 23 2014Sept 25 2014

Publication series

NameProceedings - 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014

Other

Other2014 8th IEEE International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014
Country/TerritoryJapan
CityAizu-Wakamatsu
Period9/23/149/25/14

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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