Phase optimization in technology mapping

Research output: Contribution to journalArticle

Abstract

Though tree covering is an efficient algorithm for technology mapping, phase assignments on tree boundaries are not taken into consideration. Several inverter minimization algorithms have been proposed so far, but they do phase optimization before or after technology mapping, and their cost function is not to minimize the total area but to minimize the number of inverters. This paper describes a new formulation of phase optimization problem aiming to minimize the total area during the technology mapping. Cost function representing area according to each phase assignment is introduced, and tree covering algorithm is modified to handle that cost function. Edge-Valued Binary Decision Diagram is used to represent the function implicitly. Experimental results show that proposed method reduces about 10% area on average compared with a state-of-the-art logic synthesis system sis.

Original languageEnglish
Pages (from-to)1735-1741
Number of pages7
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE78-A
Issue number12
Publication statusPublished - Dec 1995
Externally publishedYes

Fingerprint

Cost functions
Trees (mathematics)
Cost Function
Optimization
Minimise
Binary decision diagrams
Assignment
Covering
Logic Synthesis
Decision Diagrams
Inverter
Efficient Algorithms
Binary
Optimization Problem
Formulation
Experimental Results

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Information Systems
  • Electrical and Electronic Engineering

Cite this

Phase optimization in technology mapping. / Matsunaga, Yusuke.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E78-A, No. 12, 12.1995, p. 1735-1741.

Research output: Contribution to journalArticle

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