Photoluminescence evaluation of defects generated during temperature ramp-up process of SiGe-on-insulator virtual substrate fabrication

Dong Wang; Seiichiro Ii; Ken Ichi Ikeda; Hideharu Nakashima; Hiroshi Nakashima

doi:10.1109/ICSICT.2006.306678

Photoluminescence evaluation of defects generated during temperature ramp-up process of SiGe-on-insulator virtual substrate fabrication

Dong Wang, Seiichiro Ii, Ken Ichi Ikeda, Hideharu Nakashima, Hiroshi Nakashima

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Defects generated during the temperature ramping process were evaluated by photoluminescence (PL) for Si/SiGe/Si-on-insulater structure, which is the typical structure for SiGe-on-insulator (SGOI) virtual substrate fabrication using the Ge condensation by dry oxidation. The free exciton peaks were clearly observed for the as grown wafers and decreased with the increase of annealing temperature. Defect-related PL signals at around 0.82, 0.88, 0.95 and 1.0 eV were observed and they also varied according to the annealing temperature and SiGe thickness. The defect-related PL signals were also correlated to dislocation-related defects by transmission electron microscopy (TEM).

Original language	English
Title of host publication	ICSICT-2006
Subtitle of host publication	2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
Pages	2193-2195
Number of pages	3
DOIs	https://doi.org/10.1109/ICSICT.2006.306678
Publication status	Published - Aug 2 2007
Event	ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology - Shanghai, China Duration: Oct 23 2006 → Oct 26 2006

Other

Other	ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology
Country/Territory	China
City	Shanghai
Period	10/23/06 → 10/26/06

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ICSICT.2006.306678

Cite this

Wang, D., Ii, S., Ikeda, K. I., Nakashima, H., & Nakashima, H. (2007). Photoluminescence evaluation of defects generated during temperature ramp-up process of SiGe-on-insulator virtual substrate fabrication. In ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings (pp. 2193-2195). [4098665] https://doi.org/10.1109/ICSICT.2006.306678

Photoluminescence evaluation of defects generated during temperature ramp-up process of SiGe-on-insulator virtual substrate fabrication. / Wang, Dong; Ii, Seiichiro; Ikeda, Ken Ichi et al.
ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2007. p. 2193-2195 4098665.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Wang, D, Ii, S, Ikeda, KI, Nakashima, H & Nakashima, H 2007, Photoluminescence evaluation of defects generated during temperature ramp-up process of SiGe-on-insulator virtual substrate fabrication. in ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings., 4098665, pp. 2193-2195, ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Shanghai, China, 10/23/06. https://doi.org/10.1109/ICSICT.2006.306678

@inproceedings{87932aa5834a46ff9852175af787475e,

title = "Photoluminescence evaluation of defects generated during temperature ramp-up process of SiGe-on-insulator virtual substrate fabrication",

abstract = "Defects generated during the temperature ramping process were evaluated by photoluminescence (PL) for Si/SiGe/Si-on-insulater structure, which is the typical structure for SiGe-on-insulator (SGOI) virtual substrate fabrication using the Ge condensation by dry oxidation. The free exciton peaks were clearly observed for the as grown wafers and decreased with the increase of annealing temperature. Defect-related PL signals at around 0.82, 0.88, 0.95 and 1.0 eV were observed and they also varied according to the annealing temperature and SiGe thickness. The defect-related PL signals were also correlated to dislocation-related defects by transmission electron microscopy (TEM).",

author = "Dong Wang and Seiichiro Ii and Ikeda, {Ken Ichi} and Hideharu Nakashima and Hiroshi Nakashima",

year = "2007",

month = aug,

day = "2",

doi = "10.1109/ICSICT.2006.306678",

language = "English",

isbn = "1424401615",

pages = "2193--2195",

booktitle = "ICSICT-2006",

note = "ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology ; Conference date: 23-10-2006 Through 26-10-2006",

}

TY - GEN

T1 - Photoluminescence evaluation of defects generated during temperature ramp-up process of SiGe-on-insulator virtual substrate fabrication

AU - Wang, Dong

AU - Ii, Seiichiro

AU - Ikeda, Ken Ichi

AU - Nakashima, Hideharu

AU - Nakashima, Hiroshi

PY - 2007/8/2

Y1 - 2007/8/2

N2 - Defects generated during the temperature ramping process were evaluated by photoluminescence (PL) for Si/SiGe/Si-on-insulater structure, which is the typical structure for SiGe-on-insulator (SGOI) virtual substrate fabrication using the Ge condensation by dry oxidation. The free exciton peaks were clearly observed for the as grown wafers and decreased with the increase of annealing temperature. Defect-related PL signals at around 0.82, 0.88, 0.95 and 1.0 eV were observed and they also varied according to the annealing temperature and SiGe thickness. The defect-related PL signals were also correlated to dislocation-related defects by transmission electron microscopy (TEM).

AB - Defects generated during the temperature ramping process were evaluated by photoluminescence (PL) for Si/SiGe/Si-on-insulater structure, which is the typical structure for SiGe-on-insulator (SGOI) virtual substrate fabrication using the Ge condensation by dry oxidation. The free exciton peaks were clearly observed for the as grown wafers and decreased with the increase of annealing temperature. Defect-related PL signals at around 0.82, 0.88, 0.95 and 1.0 eV were observed and they also varied according to the annealing temperature and SiGe thickness. The defect-related PL signals were also correlated to dislocation-related defects by transmission electron microscopy (TEM).

UR - http://www.scopus.com/inward/record.url?scp=34547301499&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34547301499&partnerID=8YFLogxK

U2 - 10.1109/ICSICT.2006.306678

DO - 10.1109/ICSICT.2006.306678

M3 - Conference contribution

SN - 1424401615

SN - 9781424401611

SP - 2193

EP - 2195

BT - ICSICT-2006

T2 - ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology

Y2 - 23 October 2006 through 26 October 2006

ER -

Photoluminescence evaluation of defects generated during temperature ramp-up process of SiGe-on-insulator virtual substrate fabrication

Abstract

Other

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this