Photoluminescence evaluation of defects generated during temperature ramp-up process of SiGe-on-insulator virtual substrate fabrication

Dong Wang, Seiichiro Ii, Ken Ichi Ikeda, Hideharu Nakashima, Hiroshi Nakashima

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Defects generated during the temperature ramping process were evaluated by photoluminescence (PL) for Si/SiGe/Si-on-insulater structure, which is the typical structure for SiGe-on-insulator (SGOI) virtual substrate fabrication using the Ge condensation by dry oxidation. The free exciton peaks were clearly observed for the as grown wafers and decreased with the increase of annealing temperature. Defect-related PL signals at around 0.82, 0.88, 0.95 and 1.0 eV were observed and they also varied according to the annealing temperature and SiGe thickness. The defect-related PL signals were also correlated to dislocation-related defects by transmission electron microscopy (TEM).

Original languageEnglish
Title of host publicationICSICT-2006
Subtitle of host publication2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
Pages2193-2195
Number of pages3
DOIs
Publication statusPublished - Aug 2 2007
EventICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology - Shanghai, China
Duration: Oct 23 2006Oct 26 2006

Other

OtherICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology
CountryChina
CityShanghai
Period10/23/0610/26/06

Fingerprint

Photoluminescence
Fabrication
Defects
Substrates
Annealing
Temperature
Excitons
Condensation
Transmission electron microscopy
Oxidation

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Wang, D., Ii, S., Ikeda, K. I., Nakashima, H., & Nakashima, H. (2007). Photoluminescence evaluation of defects generated during temperature ramp-up process of SiGe-on-insulator virtual substrate fabrication. In ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings (pp. 2193-2195). [4098665] https://doi.org/10.1109/ICSICT.2006.306678

Photoluminescence evaluation of defects generated during temperature ramp-up process of SiGe-on-insulator virtual substrate fabrication. / Wang, Dong; Ii, Seiichiro; Ikeda, Ken Ichi; Nakashima, Hideharu; Nakashima, Hiroshi.

ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2007. p. 2193-2195 4098665.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wang, D, Ii, S, Ikeda, KI, Nakashima, H & Nakashima, H 2007, Photoluminescence evaluation of defects generated during temperature ramp-up process of SiGe-on-insulator virtual substrate fabrication. in ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings., 4098665, pp. 2193-2195, ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Shanghai, China, 10/23/06. https://doi.org/10.1109/ICSICT.2006.306678
Wang D, Ii S, Ikeda KI, Nakashima H, Nakashima H. Photoluminescence evaluation of defects generated during temperature ramp-up process of SiGe-on-insulator virtual substrate fabrication. In ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2007. p. 2193-2195. 4098665 https://doi.org/10.1109/ICSICT.2006.306678
Wang, Dong ; Ii, Seiichiro ; Ikeda, Ken Ichi ; Nakashima, Hideharu ; Nakashima, Hiroshi. / Photoluminescence evaluation of defects generated during temperature ramp-up process of SiGe-on-insulator virtual substrate fabrication. ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2007. pp. 2193-2195
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