Possibilities to miss predicting timing errors in canary flip-flops

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

Deep submicron technologies increase parameter variations, which will make microprocessor designs very difficult, since every variation requires a large safety margin for achieving specified timing yield. This means higher supply voltage, which results in large energy consumption. Razor flip-flop (FF) is a clever technique to eliminate the supply voltage margin by exploiting circuit-level timing speculation. It combines dynamic voltage scaling technique with the error detection and recovery mechanism. We are studying an alternative timing-error-predicting FF, named canary FF. This paper discusses a critical issue regarding the canary FF. Detailed gate- and architectural-level co-simulations unveil that canary FF occasionally misses predicting timing errors.

Original languageEnglish
Title of host publication54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
DOIs
Publication statusPublished - Oct 13 2011
Event54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 - Seoul, Korea, Republic of
Duration: Aug 7 2011Aug 10 2011

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746

Other

Other54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
CountryKorea, Republic of
CitySeoul
Period8/7/118/10/11

Fingerprint

Flip flop circuits
Error detection
Electric potential
Microprocessor chips
Energy utilization
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Kunitake, Y., Sato, T., Yasuura, H., & Hayashida, T. (2011). Possibilities to miss predicting timing errors in canary flip-flops. In 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 [6026656] (Midwest Symposium on Circuits and Systems). https://doi.org/10.1109/MWSCAS.2011.6026656

Possibilities to miss predicting timing errors in canary flip-flops. / Kunitake, Yuji; Sato, Toshinori; Yasuura, Hiroto; Hayashida, Takanori.

54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011. 2011. 6026656 (Midwest Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kunitake, Y, Sato, T, Yasuura, H & Hayashida, T 2011, Possibilities to miss predicting timing errors in canary flip-flops. in 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011., 6026656, Midwest Symposium on Circuits and Systems, 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011, Seoul, Korea, Republic of, 8/7/11. https://doi.org/10.1109/MWSCAS.2011.6026656
Kunitake Y, Sato T, Yasuura H, Hayashida T. Possibilities to miss predicting timing errors in canary flip-flops. In 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011. 2011. 6026656. (Midwest Symposium on Circuits and Systems). https://doi.org/10.1109/MWSCAS.2011.6026656
Kunitake, Yuji ; Sato, Toshinori ; Yasuura, Hiroto ; Hayashida, Takanori. / Possibilities to miss predicting timing errors in canary flip-flops. 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011. 2011. (Midwest Symposium on Circuits and Systems).
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