Post-layout simulation time reduction for phase-locked loop frequency synthesizer using system identification techniques

Lechang Liu, Ramesh Pokharel

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Compact model extraction of phase-locked loop (PLL) frequency synthesizer using system identification techniques is proposed to reduce post-layout simulation time. This is the first published compact model for PLL using system identification techniques. It features an autoregressive exogenous model for the charge pump and the loop filter with a lookup table for nonlinearity compensation and a radial basis function neural network for the voltage-controlled oscillator with nonlinear frequency-voltage relationship, thereby reducing the post-layout simulation time to 26% of the original circuits with the accuracy of 93%.

Original languageEnglish
Article number6926919
Pages (from-to)1751-1755
Number of pages5
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume33
Issue number11
DOIs
Publication statusPublished - Nov 1 2014

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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