Power Analysis and Estimation for SOC Design

Techniques and Tools

Research output: Contribution to journalReview article

Abstract

As power consumption becoming a critical concern for System-On-a-Chip (SOC) design, accurate and efficient power analysis and estimation during the design phase at all levels of abstraction are becoming increasingly pressing in order to achieve low power without a costly redesign process. This paper surveys analysis and estimation techniques of dynamic power and leakage power for SOC design covering multiple design levels, which have been recently proposed, aiming to present a cohesive view of the power estimation techniques at all design levels of abstraction.

Original languageEnglish
Pages (from-to)410-416
Number of pages7
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE87-A
Issue number2
Publication statusPublished - Jan 1 2004

Fingerprint

Power Analysis
Chip
Leakage
Power Consumption
Electric power utilization
Covering
Design

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

Cite this

Power Analysis and Estimation for SOC Design : Techniques and Tools. / Cao, Yun; Yasuura, Hiroto.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E87-A, No. 2, 01.01.2004, p. 410-416.

Research output: Contribution to journalReview article

@article{74b8e19b6d4346bca1fcf22398d40db2,
title = "Power Analysis and Estimation for SOC Design: Techniques and Tools",
abstract = "As power consumption becoming a critical concern for System-On-a-Chip (SOC) design, accurate and efficient power analysis and estimation during the design phase at all levels of abstraction are becoming increasingly pressing in order to achieve low power without a costly redesign process. This paper surveys analysis and estimation techniques of dynamic power and leakage power for SOC design covering multiple design levels, which have been recently proposed, aiming to present a cohesive view of the power estimation techniques at all design levels of abstraction.",
author = "Yun Cao and Hiroto Yasuura",
year = "2004",
month = "1",
day = "1",
language = "English",
volume = "E87-A",
pages = "410--416",
journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
issn = "0916-8508",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "2",

}

TY - JOUR

T1 - Power Analysis and Estimation for SOC Design

T2 - Techniques and Tools

AU - Cao, Yun

AU - Yasuura, Hiroto

PY - 2004/1/1

Y1 - 2004/1/1

N2 - As power consumption becoming a critical concern for System-On-a-Chip (SOC) design, accurate and efficient power analysis and estimation during the design phase at all levels of abstraction are becoming increasingly pressing in order to achieve low power without a costly redesign process. This paper surveys analysis and estimation techniques of dynamic power and leakage power for SOC design covering multiple design levels, which have been recently proposed, aiming to present a cohesive view of the power estimation techniques at all design levels of abstraction.

AB - As power consumption becoming a critical concern for System-On-a-Chip (SOC) design, accurate and efficient power analysis and estimation during the design phase at all levels of abstraction are becoming increasingly pressing in order to achieve low power without a costly redesign process. This paper surveys analysis and estimation techniques of dynamic power and leakage power for SOC design covering multiple design levels, which have been recently proposed, aiming to present a cohesive view of the power estimation techniques at all design levels of abstraction.

UR - http://www.scopus.com/inward/record.url?scp=1442357392&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=1442357392&partnerID=8YFLogxK

M3 - Review article

VL - E87-A

SP - 410

EP - 416

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

SN - 0916-8508

IS - 2

ER -