Power analysis techniques for SoC with improved wiring models

Takeshi Sakamoto; Takashi Yamada; Mamoru Mukuno; Yoshifumi Matsushita; Yasoo Harada; Hiroto Yasuura

doi:10.1109/lpe.2002.146750

Power analysis techniques for SoC with improved wiring models

Takeshi Sakamoto, Takashi Yamada, Mamoru Mukuno, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura

Trustee(Vice President)

Research output: Contribution to conference › Paper › peer-review

2 Citations (Scopus)

Abstract

This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) The creation of custom wire load models for clock nets (2) The use of layout information (actual net capacitance and input signal transition time) The analysis time is reduced to less than one three-hundredth of the transistor-level power analysis time. The error is within 5% of that of a real chip, (the same level in transistor-level power analysis) if technique (2) is used. The analytical error between technique (1) and (2) is within 1%.

Original language	English
Pages	259-262
Number of pages	4
DOIs	https://doi.org/10.1109/lpe.2002.146750
Publication status	Published - 2002
Event	Proceedings of the 2002 International Symposium on Low Power Electronics and Design - Monterey, CA, United States Duration: Aug 12 2002 → Aug 14 2002

Other

Other	Proceedings of the 2002 International Symposium on Low Power Electronics and Design
Country/Territory	United States
City	Monterey, CA
Period	8/12/02 → 8/14/02

All Science Journal Classification (ASJC) codes

Engineering(all)

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10.1109/lpe.2002.146750

Cite this

Power analysis techniques for SoC with improved wiring models. / Sakamoto, Takeshi; Yamada, Takashi; Mukuno, Mamoru; Matsushita, Yoshifumi; Harada, Yasoo; Yasuura, Hiroto.

2002. 259-262 Paper presented at Proceedings of the 2002 International Symposium on Low Power Electronics and Design, Monterey, CA, United States.

Research output: Contribution to conference › Paper › peer-review

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title = "Power analysis techniques for SoC with improved wiring models",

abstract = "This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) The creation of custom wire load models for clock nets (2) The use of layout information (actual net capacitance and input signal transition time) The analysis time is reduced to less than one three-hundredth of the transistor-level power analysis time. The error is within 5% of that of a real chip, (the same level in transistor-level power analysis) if technique (2) is used. The analytical error between technique (1) and (2) is within 1%.",

author = "Takeshi Sakamoto and Takashi Yamada and Mamoru Mukuno and Yoshifumi Matsushita and Yasoo Harada and Hiroto Yasuura",

year = "2002",

doi = "10.1109/lpe.2002.146750",

language = "English",

pages = "259--262",

note = "Proceedings of the 2002 International Symposium on Low Power Electronics and Design ; Conference date: 12-08-2002 Through 14-08-2002",

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T1 - Power analysis techniques for SoC with improved wiring models

AU - Sakamoto, Takeshi

AU - Yamada, Takashi

AU - Mukuno, Mamoru

AU - Matsushita, Yoshifumi

AU - Harada, Yasoo

AU - Yasuura, Hiroto

PY - 2002

Y1 - 2002

N2 - This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) The creation of custom wire load models for clock nets (2) The use of layout information (actual net capacitance and input signal transition time) The analysis time is reduced to less than one three-hundredth of the transistor-level power analysis time. The error is within 5% of that of a real chip, (the same level in transistor-level power analysis) if technique (2) is used. The analytical error between technique (1) and (2) is within 1%.

AB - This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) The creation of custom wire load models for clock nets (2) The use of layout information (actual net capacitance and input signal transition time) The analysis time is reduced to less than one three-hundredth of the transistor-level power analysis time. The error is within 5% of that of a real chip, (the same level in transistor-level power analysis) if technique (2) is used. The analytical error between technique (1) and (2) is within 1%.

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DO - 10.1109/lpe.2002.146750

M3 - Paper

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SP - 259

EP - 262

T2 - Proceedings of the 2002 International Symposium on Low Power Electronics and Design

Y2 - 11 August 2002 through 13 August 2002

ER -

Power analysis techniques for SoC with improved wiring models

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