Power analysis techniques for SoC with improved wiring models

Takeshi Sakamoto, Takashi Yamada, Mamoru Mukuno, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura

Research output: Contribution to conferencePaper

2 Citations (Scopus)

Abstract

This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) The creation of custom wire load models for clock nets (2) The use of layout information (actual net capacitance and input signal transition time) The analysis time is reduced to less than one three-hundredth of the transistor-level power analysis time. The error is within 5% of that of a real chip, (the same level in transistor-level power analysis) if technique (2) is used. The analytical error between technique (1) and (2) is within 1%.

Original languageEnglish
Pages259-262
Number of pages4
Publication statusPublished - Dec 1 2002
EventProceedings of the 2002 International Symposium on Low Power Electronics and Design - Monterey, CA, United States
Duration: Aug 12 2002Aug 14 2002

Other

OtherProceedings of the 2002 International Symposium on Low Power Electronics and Design
CountryUnited States
CityMonterey, CA
Period8/12/028/14/02

Fingerprint

Electric wiring
Transistors
Clocks
Capacitance
Wire

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Sakamoto, T., Yamada, T., Mukuno, M., Matsushita, Y., Harada, Y., & Yasuura, H. (2002). Power analysis techniques for SoC with improved wiring models. 259-262. Paper presented at Proceedings of the 2002 International Symposium on Low Power Electronics and Design, Monterey, CA, United States.

Power analysis techniques for SoC with improved wiring models. / Sakamoto, Takeshi; Yamada, Takashi; Mukuno, Mamoru; Matsushita, Yoshifumi; Harada, Yasoo; Yasuura, Hiroto.

2002. 259-262 Paper presented at Proceedings of the 2002 International Symposium on Low Power Electronics and Design, Monterey, CA, United States.

Research output: Contribution to conferencePaper

Sakamoto, T, Yamada, T, Mukuno, M, Matsushita, Y, Harada, Y & Yasuura, H 2002, 'Power analysis techniques for SoC with improved wiring models' Paper presented at Proceedings of the 2002 International Symposium on Low Power Electronics and Design, Monterey, CA, United States, 8/12/02 - 8/14/02, pp. 259-262.
Sakamoto T, Yamada T, Mukuno M, Matsushita Y, Harada Y, Yasuura H. Power analysis techniques for SoC with improved wiring models. 2002. Paper presented at Proceedings of the 2002 International Symposium on Low Power Electronics and Design, Monterey, CA, United States.
Sakamoto, Takeshi ; Yamada, Takashi ; Mukuno, Mamoru ; Matsushita, Yoshifumi ; Harada, Yasoo ; Yasuura, Hiroto. / Power analysis techniques for SoC with improved wiring models. Paper presented at Proceedings of the 2002 International Symposium on Low Power Electronics and Design, Monterey, CA, United States.4 p.
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