This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) The creation of custom wire load models for clock nets (2) The use of layout information (actual net capacitance and input signal transition time) The analysis time is reduced to less than one three-hundredth of the transistor-level power analysis time. The error is within 5% of that of a real chip, (the same level in transistor-level power analysis) if technique (2) is used. The analytical error between technique (1) and (2) is within 1%.
|Number of pages||4|
|Publication status||Published - 2002|
|Event||Proceedings of the 2002 International Symposium on Low Power Electronics and Design - Monterey, CA, United States|
Duration: Aug 12 2002 → Aug 14 2002
|Other||Proceedings of the 2002 International Symposium on Low Power Electronics and Design|
|Period||8/12/02 → 8/14/02|
All Science Journal Classification (ASJC) codes