Abstract
This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) The creation of custom wire load models for clock nets (2) The use of layout information (actual net capacitance and input signal transition time) The analysis time is reduced to less than one three-hundredth of the transistor-level power analysis time. The error is within 5% of that of a real chip, (the same level in transistor-level power analysis) if technique (2) is used. The analytical error between technique (1) and (2) is within 1%.
| Original language | English |
|---|---|
| Pages | 259-262 |
| Number of pages | 4 |
| Publication status | Published - Dec 1 2002 |
| Event | Proceedings of the 2002 International Symposium on Low Power Electronics and Design - Monterey, CA, United States Duration: Aug 12 2002 → Aug 14 2002 |
Other
| Other | Proceedings of the 2002 International Symposium on Low Power Electronics and Design |
|---|---|
| Country | United States |
| City | Monterey, CA |
| Period | 8/12/02 → 8/14/02 |
Fingerprint
All Science Journal Classification (ASJC) codes
- Engineering(all)
Cite this
Power analysis techniques for SoC with improved wiring models. / Sakamoto, Takeshi; Yamada, Takashi; Mukuno, Mamoru; Matsushita, Yoshifumi; Harada, Yasoo; Yasuura, Hiroto.
2002. 259-262 Paper presented at Proceedings of the 2002 International Symposium on Low Power Electronics and Design, Monterey, CA, United States.Research output: Contribution to conference › Paper
}
TY - CONF
T1 - Power analysis techniques for SoC with improved wiring models
AU - Sakamoto, Takeshi
AU - Yamada, Takashi
AU - Mukuno, Mamoru
AU - Matsushita, Yoshifumi
AU - Harada, Yasoo
AU - Yasuura, Hiroto
PY - 2002/12/1
Y1 - 2002/12/1
N2 - This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) The creation of custom wire load models for clock nets (2) The use of layout information (actual net capacitance and input signal transition time) The analysis time is reduced to less than one three-hundredth of the transistor-level power analysis time. The error is within 5% of that of a real chip, (the same level in transistor-level power analysis) if technique (2) is used. The analytical error between technique (1) and (2) is within 1%.
AB - This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) The creation of custom wire load models for clock nets (2) The use of layout information (actual net capacitance and input signal transition time) The analysis time is reduced to less than one three-hundredth of the transistor-level power analysis time. The error is within 5% of that of a real chip, (the same level in transistor-level power analysis) if technique (2) is used. The analytical error between technique (1) and (2) is within 1%.
UR - http://www.scopus.com/inward/record.url?scp=0036949556&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0036949556&partnerID=8YFLogxK
M3 - Paper
AN - SCOPUS:0036949556
SP - 259
EP - 262
ER -