Power-aware test generation for reducing yield loss risk in at-speed scan testing

Y. Yamato, X. Wen, K. Miyase, Hiroshi Furukawa, S. Kajihara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Power-aware X-filling is a preferable approach to avoiding IR-drop-induced yield loss in at-speed scan testing without the need of any circuit modification. However, the effect achieved by previous X-filling methods for reducing launch switching activity may be far from optimal. In addition, some of them are not scalable. This paper proposes a new X-filling method based on the genetic algorithm (GA). Experimental results on benchmark circuits demonstrate the effectiveness and scalability of the new X-filling method for reducing launch switching activity.

Original languageEnglish
Title of host publicationECS Transactions - ISTC/CSTIC 2009 (CISTC)
Pages231-236
Number of pages6
Edition1 PART 1
DOIs
Publication statusPublished - Dec 1 2009
EventISTC/CSTIC 2009 (CISTC) - Shanghai, China
Duration: Mar 19 2009Mar 20 2009

Publication series

NameECS Transactions
Number1 PART 1
Volume18
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

OtherISTC/CSTIC 2009 (CISTC)
CountryChina
CityShanghai
Period3/19/093/20/09

Fingerprint

Testing
Networks (circuits)
Scalability
Genetic algorithms

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Yamato, Y., Wen, X., Miyase, K., Furukawa, H., & Kajihara, S. (2009). Power-aware test generation for reducing yield loss risk in at-speed scan testing. In ECS Transactions - ISTC/CSTIC 2009 (CISTC) (1 PART 1 ed., pp. 231-236). (ECS Transactions; Vol. 18, No. 1 PART 1). https://doi.org/10.1149/1.3096455

Power-aware test generation for reducing yield loss risk in at-speed scan testing. / Yamato, Y.; Wen, X.; Miyase, K.; Furukawa, Hiroshi; Kajihara, S.

ECS Transactions - ISTC/CSTIC 2009 (CISTC). 1 PART 1. ed. 2009. p. 231-236 (ECS Transactions; Vol. 18, No. 1 PART 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yamato, Y, Wen, X, Miyase, K, Furukawa, H & Kajihara, S 2009, Power-aware test generation for reducing yield loss risk in at-speed scan testing. in ECS Transactions - ISTC/CSTIC 2009 (CISTC). 1 PART 1 edn, ECS Transactions, no. 1 PART 1, vol. 18, pp. 231-236, ISTC/CSTIC 2009 (CISTC), Shanghai, China, 3/19/09. https://doi.org/10.1149/1.3096455
Yamato Y, Wen X, Miyase K, Furukawa H, Kajihara S. Power-aware test generation for reducing yield loss risk in at-speed scan testing. In ECS Transactions - ISTC/CSTIC 2009 (CISTC). 1 PART 1 ed. 2009. p. 231-236. (ECS Transactions; 1 PART 1). https://doi.org/10.1149/1.3096455
Yamato, Y. ; Wen, X. ; Miyase, K. ; Furukawa, Hiroshi ; Kajihara, S. / Power-aware test generation for reducing yield loss risk in at-speed scan testing. ECS Transactions - ISTC/CSTIC 2009 (CISTC). 1 PART 1. ed. 2009. pp. 231-236 (ECS Transactions; 1 PART 1).
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