Power-Efficient Breadth-First Search with DRAM Row Buffer Locality-Aware Address Mapping

Satoshi Imamura, Yuichiro Yasui, Koji Inoue, Takatsugu Ono, Hiroshi Sasaki, Katsuki Fujisawa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Graph analysis applications have been widely used in real services such as road-traffic analysis and social network services. Breadth-first search (BFS) is one of the most representative algorithms for such applications; therefore, many researchers have tuned it to maximize performance. On the other hand, owing to the strict power constraints of modern HPC systems, it is necessary to improve power efficiency (i.e., performance per watt) when executing BFS. In this work, we focus on the power efficiency of DRAM and investigate the memory access pattern of a state-of-the-art BFS implementation using a cycle-accurate processor simulator. The results reveal that the conventional address mapping schemes of modern memory controllers do not efficiently exploit row buffers in DRAM. Thus, we propose a new scheme called per-row channel interleaving and improve the DRAM power efficiency by 30.3% compared to a conventional scheme for a certain simulator setting. Moreover, we demonstrate that this proposed scheme is effective for various configurations of memory controllers.

Original languageEnglish
Title of host publicationProceedings of HPGDMP 2016
Subtitle of host publicationHigh Performance Graph Data Management and Processing - Held in conjunction with SC 2016: The International Conference for High Performance Computing, Networking, Storage and Analysis
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages17-24
Number of pages8
ISBN (Electronic)9781509038800
DOIs
Publication statusPublished - Jan 23 2017
Event2016 High Performance Graph Data Management and Processing, HPGDMP 2016 - Salt Lake City, United States
Duration: Nov 13 2016 → …

Publication series

NameProceedings of HPGDMP 2016: High Performance Graph Data Management and Processing - Held in conjunction with SC 2016: The International Conference for High Performance Computing, Networking, Storage and Analysis

Other

Other2016 High Performance Graph Data Management and Processing, HPGDMP 2016
CountryUnited States
CitySalt Lake City
Period11/13/16 → …

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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    Imamura, S., Yasui, Y., Inoue, K., Ono, T., Sasaki, H., & Fujisawa, K. (2017). Power-Efficient Breadth-First Search with DRAM Row Buffer Locality-Aware Address Mapping. In Proceedings of HPGDMP 2016: High Performance Graph Data Management and Processing - Held in conjunction with SC 2016: The International Conference for High Performance Computing, Networking, Storage and Analysis (pp. 17-24). [7830443] (Proceedings of HPGDMP 2016: High Performance Graph Data Management and Processing - Held in conjunction with SC 2016: The International Conference for High Performance Computing, Networking, Storage and Analysis). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/HPGDMP.2016.010