Practical test architecture optimization for system-on-a-chip under floorplanning constraints

Makoto Sugihara, Kazuaki Murakami, Yusuke Matsunaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In testing system-on-a-chip (SOC), external pins for test are getting more and more precious hardware resources because the number of external pins is strongly restricted. Cores, which are basic components to build SOCs, are tested via test access mechanisms (TAMs) such as a test bus architecture. When cores are tested via TAMs, test stimuli and test responses for cores have to be transported over these TAMs. There is often the difference between the numbers of input/output ports of cores and the widths of TAMs. This difference causes the serialization of test patterns. It is probable that some parts of TAMs are unused because of the difference. This is a wasteful usage of TAMs. Test scheduling should be done in order to remove such a wasteful usage of TAMs. In this paper, a novel and practical test architecture optimization is proposed such that test time is minimized with floorplanning constraints abided. In this proposal, the computation time for the optimization can be alleviated by floorplanning manipulation. Several experimental results to this optimization are shown to validate this proposal using a commercial LP solver.

Original languageEnglish
Title of host publicationProceedings - IEEE Computer Society Annual Symposium on VLSI
Subtitle of host publicationEmerging Trends in VLSI Systems Design
EditorsA. Smailagic, M. Bayoumi
Pages179-184
Number of pages6
DOIs
Publication statusPublished - Sep 24 2004
EventProceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design - Lafayette, LA, United States
Duration: Feb 19 2004Feb 20 2004

Publication series

NameProceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design

Other

OtherProceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design
CountryUnited States
CityLafayette, LA
Period2/19/042/20/04

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Sugihara, M., Murakami, K., & Matsunaga, Y. (2004). Practical test architecture optimization for system-on-a-chip under floorplanning constraints. In A. Smailagic, & M. Bayoumi (Eds.), Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (pp. 179-184). (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design). https://doi.org/10.1109/ISVLSI.2004.1339527