Pre-route power analysis techniques for SoC

Takashi Yamada, Takeshi Sakamoto, Shinji Furuichi, Mamoru Mukuno, Yoshifumi Matsushita, Hiroto Yasuura

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)

Abstract

This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) Creation of custom wire load models for clock nets (2) Use of layout information (actual net capacitance and input signal transition time) The analysis time is reduced to less than one three-hundredth of the transistor-level power analysis time. Error is within 5% against a real chip, (the same level as that of the transistor-level power analysis), if technique (2) is used, and within 15% if technique (1) is used.

Original languageEnglish
Pages (from-to)686-692
Number of pages7
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE86-A
Issue number3
Publication statusPublished - Mar 2003

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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