Pre-route power analysis techniques for SoC

Takashi Yamada, Takeshi Sakamoto, Shinji Furuichi, Mamoru Mukuno, Yoshifumi Matsushita, Hiroto Yasuura

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) Creation of custom wire load models for clock nets (2) Use of layout information (actual net capacitance and input signal transition time) The analysis time is reduced to less than one three-hundredth of the transistor-level power analysis time. Error is within 5% against a real chip, (the same level as that of the transistor-level power analysis), if technique (2) is used, and within 15% if technique (1) is used.

Original languageEnglish
Pages (from-to)686-692
Number of pages7
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE86-A
Issue number3
Publication statusPublished - Jan 1 2003

Fingerprint

Power Analysis
Transistors
Chip
Clocks
Capacitance
Wire
Layout
Model

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

Cite this

Yamada, T., Sakamoto, T., Furuichi, S., Mukuno, M., Matsushita, Y., & Yasuura, H. (2003). Pre-route power analysis techniques for SoC. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E86-A(3), 686-692.

Pre-route power analysis techniques for SoC. / Yamada, Takashi; Sakamoto, Takeshi; Furuichi, Shinji; Mukuno, Mamoru; Matsushita, Yoshifumi; Yasuura, Hiroto.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E86-A, No. 3, 01.01.2003, p. 686-692.

Research output: Contribution to journalArticle

Yamada, T, Sakamoto, T, Furuichi, S, Mukuno, M, Matsushita, Y & Yasuura, H 2003, 'Pre-route power analysis techniques for SoC', IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E86-A, no. 3, pp. 686-692.
Yamada, Takashi ; Sakamoto, Takeshi ; Furuichi, Shinji ; Mukuno, Mamoru ; Matsushita, Yoshifumi ; Yasuura, Hiroto. / Pre-route power analysis techniques for SoC. In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2003 ; Vol. E86-A, No. 3. pp. 686-692.
@article{12703e6141154cff9ec1ebdae82db87e,
title = "Pre-route power analysis techniques for SoC",
abstract = "This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) Creation of custom wire load models for clock nets (2) Use of layout information (actual net capacitance and input signal transition time) The analysis time is reduced to less than one three-hundredth of the transistor-level power analysis time. Error is within 5{\%} against a real chip, (the same level as that of the transistor-level power analysis), if technique (2) is used, and within 15{\%} if technique (1) is used.",
author = "Takashi Yamada and Takeshi Sakamoto and Shinji Furuichi and Mamoru Mukuno and Yoshifumi Matsushita and Hiroto Yasuura",
year = "2003",
month = "1",
day = "1",
language = "English",
volume = "E86-A",
pages = "686--692",
journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
issn = "0916-8508",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "3",

}

TY - JOUR

T1 - Pre-route power analysis techniques for SoC

AU - Yamada, Takashi

AU - Sakamoto, Takeshi

AU - Furuichi, Shinji

AU - Mukuno, Mamoru

AU - Matsushita, Yoshifumi

AU - Yasuura, Hiroto

PY - 2003/1/1

Y1 - 2003/1/1

N2 - This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) Creation of custom wire load models for clock nets (2) Use of layout information (actual net capacitance and input signal transition time) The analysis time is reduced to less than one three-hundredth of the transistor-level power analysis time. Error is within 5% against a real chip, (the same level as that of the transistor-level power analysis), if technique (2) is used, and within 15% if technique (1) is used.

AB - This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) Creation of custom wire load models for clock nets (2) Use of layout information (actual net capacitance and input signal transition time) The analysis time is reduced to less than one three-hundredth of the transistor-level power analysis time. Error is within 5% against a real chip, (the same level as that of the transistor-level power analysis), if technique (2) is used, and within 15% if technique (1) is used.

UR - http://www.scopus.com/inward/record.url?scp=0037697862&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0037697862&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0037697862

VL - E86-A

SP - 686

EP - 692

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

SN - 0916-8508

IS - 3

ER -