Pyramid bumps for fine-pitch chip-stack interconnection

Naoya Watanabe, Youhei Ootani, Tanemasa Asano

Research output: Contribution to journalArticlepeer-review

15 Citations (Scopus)

Abstract

We propose pyramid bumps as one of the compliant bumps for realizing stacked chips with fine-pitch chip interconnections. The pyramid bumps, made of Au, are fabricated by the bump transfer method. The bump size is approximately 13 μm at the base and pitch is 20 μm. A comparative study between the pyramid bump and the conventional plated bump is carried out. It is demonstrated that the pyramid bump deforms more easily than the plated bump. This indicates that the pyramid bump has a significant advantage over the plated bump in compensating the bump height deviation and the nonuniformity in bonding pressure and that the bonding of a pyramid bump can be achieved at smaller pressing loads than those necessary for a plated bump. It is also found that the pyramid bump effectively excludes insulating resin, which is precoated on the chip surface, from the bonding interface and thereby suppresses bonding failure.

Original languageEnglish
Pages (from-to)2751-2755
Number of pages5
JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume44
Issue number4 B
DOIs
Publication statusPublished - Apr 1 2005

All Science Journal Classification (ASJC) codes

  • Engineering(all)
  • Physics and Astronomy(all)

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