Real-time unified architecture for forward/inverse discrete cosine transform in high efficiency video coding

Maher Abdelrasoul, Mohammed S. Sayed, Victor Mauro Goulart Ferreira

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

In High Efficiency Video Coding (HEVC) standard, higher video resolutions employ larger integer Discrete Cosine Transform (DCT)/inverse DCT (IDCT) block sizes. In this study, the authors propose two high-throughput unified DCT/IDCT architectures. The proposed architectures can process variable DCT/IDCT block sizes according to the HEVC standard. The proposed architectures were prototyped on TSMC 65 nm CMOS technology. The prototyping results show that the two unified architectures have throughput of 15.24 and 16.03 Gsps, respectively, and they can encode video sequences with resolutions up to 8 K at 120 fps and decode the same resolution at 240 fps using only one circuit for both DCT and IDCT.

Original languageEnglish
Pages (from-to)381-387
Number of pages7
JournalIET Circuits, Devices and Systems
Volume11
Issue number4
DOIs
Publication statusPublished - Jul 1 2017

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Discrete cosine transforms
Image coding
Throughput
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Real-time unified architecture for forward/inverse discrete cosine transform in high efficiency video coding. / Abdelrasoul, Maher; Sayed, Mohammed S.; Goulart Ferreira, Victor Mauro.

In: IET Circuits, Devices and Systems, Vol. 11, No. 4, 01.07.2017, p. 381-387.

Research output: Contribution to journalArticle

Abdelrasoul, Maher ; Sayed, Mohammed S. ; Goulart Ferreira, Victor Mauro. / Real-time unified architecture for forward/inverse discrete cosine transform in high efficiency video coding. In: IET Circuits, Devices and Systems. 2017 ; Vol. 11, No. 4. pp. 381-387.
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