Real-time unified architecture for forward/inverse discrete cosine transform in high efficiency video coding

Maher Abdelrasoul, Mohammed S. Sayed, Victor Goulart

    Research output: Contribution to journalArticlepeer-review

    5 Citations (Scopus)

    Abstract

    In High Efficiency Video Coding (HEVC) standard, higher video resolutions employ larger integer Discrete Cosine Transform (DCT)/inverse DCT (IDCT) block sizes. In this study, the authors propose two high-throughput unified DCT/IDCT architectures. The proposed architectures can process variable DCT/IDCT block sizes according to the HEVC standard. The proposed architectures were prototyped on TSMC 65 nm CMOS technology. The prototyping results show that the two unified architectures have throughput of 15.24 and 16.03 Gsps, respectively, and they can encode video sequences with resolutions up to 8 K at 120 fps and decode the same resolution at 240 fps using only one circuit for both DCT and IDCT.

    Original languageEnglish
    Pages (from-to)381-387
    Number of pages7
    JournalIET Circuits, Devices and Systems
    Volume11
    Issue number4
    DOIs
    Publication statusPublished - Jul 1 2017

    All Science Journal Classification (ASJC) codes

    • Control and Systems Engineering
    • Electrical and Electronic Engineering

    Fingerprint Dive into the research topics of 'Real-time unified architecture for forward/inverse discrete cosine transform in high efficiency video coding'. Together they form a unique fingerprint.

    Cite this