REDEFIS - A system with a redefinable instruction set processor

Victor M. Goulart Ferreira, Lovic Gauthier, Takayuki Kando, Takuma Matsuo, Toshihiko Hashinaga, Kazuaki Murakami

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

The growing complexity and production cost of processor-based systems have imposed big constraints in SoC design of new systems. GPPs and ASICs are unable to fit the tight performance or power constraints, or too complex to design in short TAT/TTM. REDEFIS is a HW/SW design platform for high level, efficient implementation of ASIPs/engines for SoC systems. It is composed of a reconfigurable instruction-set processor, capable to redefine its ISA according to the user application written in high level C language, and a set of design tools (an ISA Generator and a retargetable compiler). These processors can be used as flexible engines in embedded MPSoC systems, where its ISA is fully customized and design is done at high level C (no HDL writing is necessary). In this paper we present the Redefis design platform and an implementation of our dynamically reconfigurable ISA processor (codename Vulcan). Our results demonstrate the effectiveness of the system for encryption and bitwise applications. Dynamically reconfigurable processor, ISA customization, high performance, low power, SoC.

Original languageEnglish
Title of host publicationProceedings SBCCI 2006 - 19th Symposium on Integrated Circuits and Systems Design
Pages14-19
Number of pages6
Publication statusPublished - 2006
EventSBCCI 2006 - 19th Symposium on Integrated Circuits and Systems Design - Minas Gerais, Brazil
Duration: Aug 28 2006Sep 1 2006

Publication series

NameSBCCI 2006 - 19th Symposium on Integrated Circuits and Systems Design
Volume2006

Other

OtherSBCCI 2006 - 19th Symposium on Integrated Circuits and Systems Design
CountryBrazil
CityMinas Gerais
Period8/28/069/1/06

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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