Abstract
This paper presents a system-level technique for embedded processor-based systems targeting both dynamic power and leakage power reduction using datapath width optimization. By means of tuning the design parameter, datapath width tailored to a given application requirements, the processors and memories are optimized resulting in significant power reduction, not only for dynamic power but also for leakage power. In our experiments for several real embedded applications, power reduction without performance penalty is reported range from about 14.5% to 59.2% of dynamic power, and 21.5% to 66.2% of leakage power.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 291-295 |
| Number of pages | 5 |
| Volume | 2002-January |
| ISBN (Electronic) | 0780374940 |
| DOIs | |
| Publication status | Published - 2002 |
| Event | 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States Duration: Sep 25 2002 → Sep 28 2002 |
Other
| Other | 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 |
|---|---|
| Country | United States |
| City | Rochester |
| Period | 9/25/02 → 9/28/02 |
Fingerprint
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
Reducing dynamic power and leakage power for embedded systems. / Cao, Yun; Yasuura, Hiroto.
Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. Vol. 2002-January Institute of Electrical and Electronics Engineers Inc., 2002. p. 291-295 1158073.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Reducing dynamic power and leakage power for embedded systems
AU - Cao, Yun
AU - Yasuura, Hiroto
PY - 2002
Y1 - 2002
N2 - This paper presents a system-level technique for embedded processor-based systems targeting both dynamic power and leakage power reduction using datapath width optimization. By means of tuning the design parameter, datapath width tailored to a given application requirements, the processors and memories are optimized resulting in significant power reduction, not only for dynamic power but also for leakage power. In our experiments for several real embedded applications, power reduction without performance penalty is reported range from about 14.5% to 59.2% of dynamic power, and 21.5% to 66.2% of leakage power.
AB - This paper presents a system-level technique for embedded processor-based systems targeting both dynamic power and leakage power reduction using datapath width optimization. By means of tuning the design parameter, datapath width tailored to a given application requirements, the processors and memories are optimized resulting in significant power reduction, not only for dynamic power but also for leakage power. In our experiments for several real embedded applications, power reduction without performance penalty is reported range from about 14.5% to 59.2% of dynamic power, and 21.5% to 66.2% of leakage power.
UR - http://www.scopus.com/inward/record.url?scp=84949459632&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84949459632&partnerID=8YFLogxK
U2 - 10.1109/ASIC.2002.1158073
DO - 10.1109/ASIC.2002.1158073
M3 - Conference contribution
VL - 2002-January
SP - 291
EP - 295
BT - Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
PB - Institute of Electrical and Electronics Engineers Inc.
ER -