Reducing dynamic power and leakage power for embedded systems

Yun Cao; Hiroto Yasuura

doi:10.1109/ASIC.2002.1158073

Reducing dynamic power and leakage power for embedded systems

Yun Cao, Hiroto Yasuura

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper presents a system-level technique for embedded processor-based systems targeting both dynamic power and leakage power reduction using datapath width optimization. By means of tuning the design parameter, datapath width tailored to a given application requirements, the processors and memories are optimized resulting in significant power reduction, not only for dynamic power but also for leakage power. In our experiments for several real embedded applications, power reduction without performance penalty is reported range from about 14.5% to 59.2% of dynamic power, and 21.5% to 66.2% of leakage power.

Original language	English
Title of host publication	Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
Editors	John Chickanosky, Ram K. Krishnamurthy, P.R. Mukund
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	291-295
Number of pages	5
ISBN (Electronic)	0780374940
DOIs	https://doi.org/10.1109/ASIC.2002.1158073
Publication status	Published - 2002
Externally published	Yes
Event	15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States Duration: Sep 25 2002 → Sep 28 2002

Publication series

Name	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
Volume	2002-January
ISSN (Print)	1063-0988

Other

Other	15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
Country/Territory	United States
City	Rochester
Period	9/25/02 → 9/28/02

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ASIC.2002.1158073

Cite this

Cao, Y., & Yasuura, H. (2002). Reducing dynamic power and leakage power for embedded systems. In J. Chickanosky, R. K. Krishnamurthy, & P. R. Mukund (Eds.), Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 (pp. 291-295). [1158073] (Proceedings of the Annual IEEE International ASIC Conference and Exhibit; Vol. 2002-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASIC.2002.1158073

Reducing dynamic power and leakage power for embedded systems. / Cao, Yun; Yasuura, Hiroto.

Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. ed. / John Chickanosky; Ram K. Krishnamurthy; P.R. Mukund. Institute of Electrical and Electronics Engineers Inc., 2002. p. 291-295 1158073 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit; Vol. 2002-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Cao, Y & Yasuura, H 2002, Reducing dynamic power and leakage power for embedded systems. in J Chickanosky, RK Krishnamurthy & PR Mukund (eds), Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002., 1158073, Proceedings of the Annual IEEE International ASIC Conference and Exhibit, vol. 2002-January, Institute of Electrical and Electronics Engineers Inc., pp. 291-295, 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002, Rochester, United States, 9/25/02. https://doi.org/10.1109/ASIC.2002.1158073

Cao Y, Yasuura H. Reducing dynamic power and leakage power for embedded systems. In Chickanosky J, Krishnamurthy RK, Mukund PR, editors, Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 291-295. 1158073. (Proceedings of the Annual IEEE International ASIC Conference and Exhibit). doi: 10.1109/ASIC.2002.1158073

Cao, Yun ; Yasuura, Hiroto. / Reducing dynamic power and leakage power for embedded systems. Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. editor / John Chickanosky ; Ram K. Krishnamurthy ; P.R. Mukund. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 291-295 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit).

@inproceedings{e7cb59a6ff0847dd84d5a54c804b54c7,

title = "Reducing dynamic power and leakage power for embedded systems",

abstract = "This paper presents a system-level technique for embedded processor-based systems targeting both dynamic power and leakage power reduction using datapath width optimization. By means of tuning the design parameter, datapath width tailored to a given application requirements, the processors and memories are optimized resulting in significant power reduction, not only for dynamic power but also for leakage power. In our experiments for several real embedded applications, power reduction without performance penalty is reported range from about 14.5% to 59.2% of dynamic power, and 21.5% to 66.2% of leakage power.",

author = "Yun Cao and Hiroto Yasuura",

note = "Publisher Copyright: {\textcopyright} 2002 IEEE.; 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 ; Conference date: 25-09-2002 Through 28-09-2002",

year = "2002",

doi = "10.1109/ASIC.2002.1158073",

language = "English",

series = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "291--295",

editor = "John Chickanosky and Krishnamurthy, {Ram K.} and P.R. Mukund",

booktitle = "Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002",

address = "United States",

}

TY - GEN

T1 - Reducing dynamic power and leakage power for embedded systems

AU - Cao, Yun

AU - Yasuura, Hiroto

PY - 2002

Y1 - 2002

N2 - This paper presents a system-level technique for embedded processor-based systems targeting both dynamic power and leakage power reduction using datapath width optimization. By means of tuning the design parameter, datapath width tailored to a given application requirements, the processors and memories are optimized resulting in significant power reduction, not only for dynamic power but also for leakage power. In our experiments for several real embedded applications, power reduction without performance penalty is reported range from about 14.5% to 59.2% of dynamic power, and 21.5% to 66.2% of leakage power.

AB - This paper presents a system-level technique for embedded processor-based systems targeting both dynamic power and leakage power reduction using datapath width optimization. By means of tuning the design parameter, datapath width tailored to a given application requirements, the processors and memories are optimized resulting in significant power reduction, not only for dynamic power but also for leakage power. In our experiments for several real embedded applications, power reduction without performance penalty is reported range from about 14.5% to 59.2% of dynamic power, and 21.5% to 66.2% of leakage power.

UR - http://www.scopus.com/inward/record.url?scp=84949459632&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84949459632&partnerID=8YFLogxK

U2 - 10.1109/ASIC.2002.1158073

DO - 10.1109/ASIC.2002.1158073

M3 - Conference contribution

AN - SCOPUS:84949459632

T3 - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

SP - 291

EP - 295

BT - Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002

A2 - Chickanosky, John

A2 - Krishnamurthy, Ram K.

A2 - Mukund, P.R.

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002

Y2 - 25 September 2002 through 28 September 2002

ER -

Reducing dynamic power and leakage power for embedded systems

Abstract

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