Reducing dynamic power and leakage power for embedded systems

Yun Cao, Hiroto Yasuura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents a system-level technique for embedded processor-based systems targeting both dynamic power and leakage power reduction using datapath width optimization. By means of tuning the design parameter, datapath width tailored to a given application requirements, the processors and memories are optimized resulting in significant power reduction, not only for dynamic power but also for leakage power. In our experiments for several real embedded applications, power reduction without performance penalty is reported range from about 14.5% to 59.2% of dynamic power, and 21.5% to 66.2% of leakage power.

Original languageEnglish
Title of host publicationProceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
EditorsJohn Chickanosky, Ram K. Krishnamurthy, P.R. Mukund
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages291-295
Number of pages5
ISBN (Electronic)0780374940
DOIs
Publication statusPublished - 2002
Event15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States
Duration: Sep 25 2002Sep 28 2002

Publication series

NameProceedings of the Annual IEEE International ASIC Conference and Exhibit
Volume2002-January
ISSN (Print)1063-0988

Other

Other15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
CountryUnited States
CityRochester
Period9/25/029/28/02

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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