TY - GEN
T1 - Reducing power consumption of instruction ROMs by exploiting instruction frequency
AU - Inoue, K.
AU - Moshnyaga, V. G.
AU - Murakami, K.
N1 - Publisher Copyright:
© 2002 IEEE.
Copyright:
Copyright 2015 Elsevier B.V., All rights reserved.
PY - 2002
Y1 - 2002
N2 - This paper proposes a new approach to reducing the power consumption of instruction ROMs for embedded systems. The power consumption of instruction ROMs strongly depends on the switching activity of bit-lines. If a read bit-value indicates '0', the precharged bitline is discharged. In this scenario, a bit-line switching takes place and consumes power. Otherwise, the precharged bit-line level is maintained until the next access, thus no bit-line switching occurs. In our approach, the binary-patterns to be assigned to op-codes are determined based on the frequency of instructions for reducing the bit-line switching activity. Application programs are analyzed in advance, and then binary-patterns including many '1's' are assigned to the most frequently referenced instructions. In our evaluation, it is observed that the proposed approach can reduce bit-line switching by 40%.
AB - This paper proposes a new approach to reducing the power consumption of instruction ROMs for embedded systems. The power consumption of instruction ROMs strongly depends on the switching activity of bit-lines. If a read bit-value indicates '0', the precharged bitline is discharged. In this scenario, a bit-line switching takes place and consumes power. Otherwise, the precharged bit-line level is maintained until the next access, thus no bit-line switching occurs. In our approach, the binary-patterns to be assigned to op-codes are determined based on the frequency of instructions for reducing the bit-line switching activity. Application programs are analyzed in advance, and then binary-patterns including many '1's' are assigned to the most frequently referenced instructions. In our evaluation, it is observed that the proposed approach can reduce bit-line switching by 40%.
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U2 - 10.1109/APCCAS.2002.1115094
DO - 10.1109/APCCAS.2002.1115094
M3 - Conference contribution
AN - SCOPUS:66849142482
T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
SP - 1
EP - 6
BT - Proceedings - APCCAS 2002
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - Asia-Pacific Conference on Circuits and Systems, APCCAS 2002
Y2 - 28 October 2002 through 31 October 2002
ER -