Reducing power consumption of instruction ROMs by exploiting instruction frequency

Inoue Koji, V. G. Moshnyaga, K. Murakami

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

This paper proposes a new approach to reducing the power consumption of instruction ROMs for embedded systems. The power consumption of instruction ROMs strongly depends on the switching activity of bit-lines. If a read bit-value indicates '0', the precharged bitline is discharged. In this scenario, a bit-line switching takes place and consumes power. Otherwise, the precharged bit-line level is maintained until the next access, thus no bit-line switching occurs. In our approach, the binary-patterns to be assigned to op-codes are determined based on the frequency of instructions for reducing the bit-line switching activity. Application programs are analyzed in advance, and then binary-patterns including many '1's' are assigned to the most frequently referenced instructions. In our evaluation, it is observed that the proposed approach can reduce bit-line switching by 40%.

Original languageEnglish
Title of host publicationProceedings - APCCAS 2002
Subtitle of host publicationAsia-Pacific Conference on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-6
Number of pages6
ISBN (Electronic)0780376900
DOIs
Publication statusPublished - Jan 1 2002
Externally publishedYes
EventAsia-Pacific Conference on Circuits and Systems, APCCAS 2002 - Denpasar, Bali, Indonesia
Duration: Oct 28 2002Oct 31 2002

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
Volume2

Other

OtherAsia-Pacific Conference on Circuits and Systems, APCCAS 2002
CountryIndonesia
CityDenpasar, Bali
Period10/28/0210/31/02

Fingerprint

ROM
Electric power utilization
Application programs
Embedded systems

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Koji, I., Moshnyaga, V. G., & Murakami, K. (2002). Reducing power consumption of instruction ROMs by exploiting instruction frequency. In Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems (pp. 1-6). [1115094] (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; Vol. 2). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2002.1115094

Reducing power consumption of instruction ROMs by exploiting instruction frequency. / Koji, Inoue; Moshnyaga, V. G.; Murakami, K.

Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2002. p. 1-6 1115094 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; Vol. 2).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Koji, I, Moshnyaga, VG & Murakami, K 2002, Reducing power consumption of instruction ROMs by exploiting instruction frequency. in Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems., 1115094, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, vol. 2, Institute of Electrical and Electronics Engineers Inc., pp. 1-6, Asia-Pacific Conference on Circuits and Systems, APCCAS 2002, Denpasar, Bali, Indonesia, 10/28/02. https://doi.org/10.1109/APCCAS.2002.1115094
Koji I, Moshnyaga VG, Murakami K. Reducing power consumption of instruction ROMs by exploiting instruction frequency. In Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc. 2002. p. 1-6. 1115094. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2002.1115094
Koji, Inoue ; Moshnyaga, V. G. ; Murakami, K. / Reducing power consumption of instruction ROMs by exploiting instruction frequency. Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 1-6 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).
@inproceedings{69c2c556ebd546e0920b75e6fac73965,
title = "Reducing power consumption of instruction ROMs by exploiting instruction frequency",
abstract = "This paper proposes a new approach to reducing the power consumption of instruction ROMs for embedded systems. The power consumption of instruction ROMs strongly depends on the switching activity of bit-lines. If a read bit-value indicates '0', the precharged bitline is discharged. In this scenario, a bit-line switching takes place and consumes power. Otherwise, the precharged bit-line level is maintained until the next access, thus no bit-line switching occurs. In our approach, the binary-patterns to be assigned to op-codes are determined based on the frequency of instructions for reducing the bit-line switching activity. Application programs are analyzed in advance, and then binary-patterns including many '1's' are assigned to the most frequently referenced instructions. In our evaluation, it is observed that the proposed approach can reduce bit-line switching by 40{\%}.",
author = "Inoue Koji and Moshnyaga, {V. G.} and K. Murakami",
year = "2002",
month = "1",
day = "1",
doi = "10.1109/APCCAS.2002.1115094",
language = "English",
series = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1--6",
booktitle = "Proceedings - APCCAS 2002",
address = "United States",

}

TY - GEN

T1 - Reducing power consumption of instruction ROMs by exploiting instruction frequency

AU - Koji, Inoue

AU - Moshnyaga, V. G.

AU - Murakami, K.

PY - 2002/1/1

Y1 - 2002/1/1

N2 - This paper proposes a new approach to reducing the power consumption of instruction ROMs for embedded systems. The power consumption of instruction ROMs strongly depends on the switching activity of bit-lines. If a read bit-value indicates '0', the precharged bitline is discharged. In this scenario, a bit-line switching takes place and consumes power. Otherwise, the precharged bit-line level is maintained until the next access, thus no bit-line switching occurs. In our approach, the binary-patterns to be assigned to op-codes are determined based on the frequency of instructions for reducing the bit-line switching activity. Application programs are analyzed in advance, and then binary-patterns including many '1's' are assigned to the most frequently referenced instructions. In our evaluation, it is observed that the proposed approach can reduce bit-line switching by 40%.

AB - This paper proposes a new approach to reducing the power consumption of instruction ROMs for embedded systems. The power consumption of instruction ROMs strongly depends on the switching activity of bit-lines. If a read bit-value indicates '0', the precharged bitline is discharged. In this scenario, a bit-line switching takes place and consumes power. Otherwise, the precharged bit-line level is maintained until the next access, thus no bit-line switching occurs. In our approach, the binary-patterns to be assigned to op-codes are determined based on the frequency of instructions for reducing the bit-line switching activity. Application programs are analyzed in advance, and then binary-patterns including many '1's' are assigned to the most frequently referenced instructions. In our evaluation, it is observed that the proposed approach can reduce bit-line switching by 40%.

UR - http://www.scopus.com/inward/record.url?scp=66849142482&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=66849142482&partnerID=8YFLogxK

U2 - 10.1109/APCCAS.2002.1115094

DO - 10.1109/APCCAS.2002.1115094

M3 - Conference contribution

T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

SP - 1

EP - 6

BT - Proceedings - APCCAS 2002

PB - Institute of Electrical and Electronics Engineers Inc.

ER -