The charge build-up of silicon-on-insulator (SOI) structures during reactive ion etching has been investigated. The charge build-up was evaluated by using metal/nitride/oxide/silicon (MNOS) capacitors fabrication on SOI. It has been found that the charge build-up can be drastically reduced by using SOI, while the reduction in etching rate is only 3% less than that attained using bulk Si wafers at a relatively high RF power condition. The amount of charge build-up has been found to decrease the thickness of the buried oxide layer increases. A model to explain these phenomena is discussed.
|Number of pages||4|
|Journal||Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers|
|Issue number||3 SUPPL. B|
|Publication status||Published - Mar 1997|
All Science Journal Classification (ASJC) codes
- Physics and Astronomy(all)