Reduction of charge build-up during reactive ion etching by using silicon-on-insulator structures

Kiyoshi Arita, Masashi Akamatsu, Tanemasa Asano

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)

Abstract

The charge build-up of silicon-on-insulator (SOI) structures during reactive ion etching has been investigated. The charge build-up was evaluated by using metal/nitride/oxide/silicon (MNOS) capacitors fabrication on SOI. It has been found that the charge build-up can be drastically reduced by using SOI, while the reduction in etching rate is only 3% less than that attained using bulk Si wafers at a relatively high RF power condition. The amount of charge build-up has been found to decrease the thickness of the buried oxide layer increases. A model to explain these phenomena is discussed.

Original languageEnglish
Pages (from-to)1505-1508
Number of pages4
JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume36
Issue number3 SUPPL. B
DOIs
Publication statusPublished - Mar 1997
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Engineering(all)
  • Physics and Astronomy(all)

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