Reduction of Coupling Effects by Optimizing the 3-D Configuration of the Routing Grid

Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

In this brief, we propose a new physical design technique for a subquarter micrometer system-on-a-chip (SoC). By optimizing the Individual layer's routing grid space, coupling effects such as crosstalk noise, crosstalk-induced delay variations, and coupling power consumption are almost eliminated with little runtime penalty. Experiments are performed on the design of an image processing circuit using a subquarter micron CMOS process with multilayer interconnects. Simply by employing our proposed technique, the maximum delay and the power consumption can be decreased simultaneously by up to 15% and 10%, respectively, without any other process improvements.

Original languageEnglish
Pages (from-to)951-954
Number of pages4
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume11
Issue number5
DOIs
Publication statusPublished - Oct 1 2003

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Crosstalk
Electric power utilization
Multilayers
Image processing
Networks (circuits)
Experiments

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Reduction of Coupling Effects by Optimizing the 3-D Configuration of the Routing Grid. / Sakai, Atsushi; Yamada, Takashi; Matsushita, Yoshifumi; Yasuura, Hiroto.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 11, No. 5, 01.10.2003, p. 951-954.

Research output: Contribution to journalArticle

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