Abstract
In this brief, we propose a new physical design technique for a subquarter micrometer system-on-a-chip (SoC). By optimizing the Individual layer's routing grid space, coupling effects such as crosstalk noise, crosstalk-induced delay variations, and coupling power consumption are almost eliminated with little runtime penalty. Experiments are performed on the design of an image processing circuit using a subquarter micron CMOS process with multilayer interconnects. Simply by employing our proposed technique, the maximum delay and the power consumption can be decreased simultaneously by up to 15% and 10%, respectively, without any other process improvements.
| Original language | English |
|---|---|
| Pages (from-to) | 951-954 |
| Number of pages | 4 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 11 |
| Issue number | 5 |
| DOIs | |
| Publication status | Published - Oct 1 2003 |
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All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
Reduction of Coupling Effects by Optimizing the 3-D Configuration of the Routing Grid. / Sakai, Atsushi; Yamada, Takashi; Matsushita, Yoshifumi; Yasuura, Hiroto.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 11, No. 5, 01.10.2003, p. 951-954.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Reduction of Coupling Effects by Optimizing the 3-D Configuration of the Routing Grid
AU - Sakai, Atsushi
AU - Yamada, Takashi
AU - Matsushita, Yoshifumi
AU - Yasuura, Hiroto
PY - 2003/10/1
Y1 - 2003/10/1
N2 - In this brief, we propose a new physical design technique for a subquarter micrometer system-on-a-chip (SoC). By optimizing the Individual layer's routing grid space, coupling effects such as crosstalk noise, crosstalk-induced delay variations, and coupling power consumption are almost eliminated with little runtime penalty. Experiments are performed on the design of an image processing circuit using a subquarter micron CMOS process with multilayer interconnects. Simply by employing our proposed technique, the maximum delay and the power consumption can be decreased simultaneously by up to 15% and 10%, respectively, without any other process improvements.
AB - In this brief, we propose a new physical design technique for a subquarter micrometer system-on-a-chip (SoC). By optimizing the Individual layer's routing grid space, coupling effects such as crosstalk noise, crosstalk-induced delay variations, and coupling power consumption are almost eliminated with little runtime penalty. Experiments are performed on the design of an image processing circuit using a subquarter micron CMOS process with multilayer interconnects. Simply by employing our proposed technique, the maximum delay and the power consumption can be decreased simultaneously by up to 15% and 10%, respectively, without any other process improvements.
UR - http://www.scopus.com/inward/record.url?scp=0142196045&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0142196045&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2003.817126
DO - 10.1109/TVLSI.2003.817126
M3 - Article
AN - SCOPUS:0142196045
VL - 11
SP - 951
EP - 954
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 5
ER -