TY - GEN
T1 - Reduction of crosstalk noise by optimizing 3-D configuration of the routing grid
AU - Sakai, A.
AU - Yamada, T.
AU - Matsushita, Y.
AU - Yasuura, H.
N1 - Publisher Copyright:
© 2003 IEEE.
PY - 2003
Y1 - 2003
N2 - In this paper, we propose novel physical design techniques for a sub-quarter micron system-on-a-chip (SoC). By appropriately optimizing the routing grid space or the cell utilization ratio, the coupling effects are almost eliminated. By employing our proposed techniques on a 0.13 μm six-layer physical design, the longest path delay is significantly decreased by 15% maximum without the need for process improvement. This significant delay reduction, which corresponds to a half generation of process progress, greatly accelerates the performance of SoCs.
AB - In this paper, we propose novel physical design techniques for a sub-quarter micron system-on-a-chip (SoC). By appropriately optimizing the routing grid space or the cell utilization ratio, the coupling effects are almost eliminated. By employing our proposed techniques on a 0.13 μm six-layer physical design, the longest path delay is significantly decreased by 15% maximum without the need for process improvement. This significant delay reduction, which corresponds to a half generation of process progress, greatly accelerates the performance of SoCs.
UR - http://www.scopus.com/inward/record.url?scp=0038791251&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0038791251&partnerID=8YFLogxK
U2 - 10.1109/ASPDAC.2003.1194992
DO - 10.1109/ASPDAC.2003.1194992
M3 - Conference contribution
AN - SCOPUS:0038791251
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 49
EP - 52
BT - Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - Asia and South Pacific Design Automation Conference, ASP-DAC 2003
Y2 - 21 January 2003 through 24 January 2003
ER -