Reduction of crosstalk noise by optimizing 3-D configuration of the routing grid

A. Sakai, T. Yamada, Y. Matsushita, H. Yasuura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, we propose novel physical design techniques for a sub-quarter micron system-on-a-chip (SoC). By appropriately optimizing the routing grid space or the cell utilization ratio, the coupling effects are almost eliminated. By employing our proposed techniques on a 0.13 μm six-layer physical design, the longest path delay is significantly decreased by 15% maximum without the need for process improvement. This significant delay reduction, which corresponds to a half generation of process progress, greatly accelerates the performance of SoCs.

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages49-52
Number of pages4
ISBN (Electronic)0780376595
DOIs
Publication statusPublished - 2003
EventAsia and South Pacific Design Automation Conference, ASP-DAC 2003 - Kitakyushu, Japan
Duration: Jan 21 2003Jan 24 2003

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2003-January

Other

OtherAsia and South Pacific Design Automation Conference, ASP-DAC 2003
CountryJapan
CityKitakyushu
Period1/21/031/24/03

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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