Register file energy reduction by operand data reuse

Hiroshi Takamura; Koji Inoue; Vasily G. Moshnyaga

doi:10.1007/3-540-45716-x_28

Register file energy reduction by operand data reuse

Hiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents an experimental study of register file utilization in conventional RISC-type data path architecture to determine benefits that we can expect to achieve by eliminating unnecessary register file reads and writes. Our analysis shows that operand bypassing, enhanced for operand-reuse can discard the register file accesses up to 65% as a peak and by 39% on average for tested benchmark programs.

Original language	English
Title of host publication	Integrated Circuit Design
Subtitle of host publication	Power and Timing Modeling, Optimization and Simulation - 12th International Workshop, PATMOS 2002, Proceedings
Editors	Bertrand Hochet, Antonio J. Acosta, Manuel J. Bellido
Publisher	Springer Verlag
Pages	278-288
Number of pages	11
ISBN (Print)	9783540441434
DOIs	https://doi.org/10.1007/3-540-45716-x_28
Publication status	Published - Jan 1 2002
Externally published	Yes
Event	12th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2002 - Seville, Spain Duration: Sept 11 2002 → Sept 13 2002

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	2451
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Other

Other	12th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2002
Country/Territory	Spain
City	Seville
Period	9/11/02 → 9/13/02

All Science Journal Classification (ASJC) codes

Theoretical Computer Science
Computer Science(all)

Access to Document

10.1007/3-540-45716-x_28

Cite this

Takamura, H., Inoue, K., & Moshnyaga, V. G. (2002). Register file energy reduction by operand data reuse. In B. Hochet, A. J. Acosta, & M. J. Bellido (Eds.), Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation - 12th International Workshop, PATMOS 2002, Proceedings (pp. 278-288). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 2451). Springer Verlag. https://doi.org/10.1007/3-540-45716-x_28

Register file energy reduction by operand data reuse. / Takamura, Hiroshi; Inoue, Koji; Moshnyaga, Vasily G.

Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation - 12th International Workshop, PATMOS 2002, Proceedings. ed. / Bertrand Hochet; Antonio J. Acosta; Manuel J. Bellido. Springer Verlag, 2002. p. 278-288 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 2451).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Takamura, H, Inoue, K & Moshnyaga, VG 2002, Register file energy reduction by operand data reuse. in B Hochet, AJ Acosta & MJ Bellido (eds), Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation - 12th International Workshop, PATMOS 2002, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 2451, Springer Verlag, pp. 278-288, 12th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2002, Seville, Spain, 9/11/02. https://doi.org/10.1007/3-540-45716-x_28

Takamura H, Inoue K, Moshnyaga VG. Register file energy reduction by operand data reuse. In Hochet B, Acosta AJ, Bellido MJ, editors, Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation - 12th International Workshop, PATMOS 2002, Proceedings. Springer Verlag. 2002. p. 278-288. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/3-540-45716-x_28

Takamura, Hiroshi ; Inoue, Koji ; Moshnyaga, Vasily G. / Register file energy reduction by operand data reuse. Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation - 12th International Workshop, PATMOS 2002, Proceedings. editor / Bertrand Hochet ; Antonio J. Acosta ; Manuel J. Bellido. Springer Verlag, 2002. pp. 278-288 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

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Register file energy reduction by operand data reuse

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