Room-temperature chip-stack interconnection using compliant bumps and wedge-incorporated electrodes

Naoya Watanabe, Tanemasa Asano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

We propose room-temperature chip-stack interconnection using mechanical caulking between compliant bumps and wedge-incorporated electrodes. In this method, cone-shaped compliant bumps made of Au are pressed into wedgeincorporated electrodes made of Au at room temperature in the ambient air. Because of the edge structures of the Au wedge incorporated electrodes, the pressing load is effectively applied to the interfaces between Au cone bumps and Au wedge-incorporated electrodes. Therefore, Au wedgeincorporated electrodes are caulked with Au cone bumps at low pressing load. By using this method, high-density interchip connections were realized at 0.50 gf/bump and 30 °C. The number of inter-chip connections realized was 30,600 with 20 μm pitch. It is also demonstrated that this method allows lower inter-chip connection resistance than the mechanical caulking between compliant bumps and doughnut-shaped electrodes

Original languageEnglish
Title of host publication2010 Proceedings 60th Electronic Components and Technology Conference, ECTC 2010
Pages1763-1768
Number of pages6
DOIs
Publication statusPublished - Aug 9 2010
Event60th Electronic Components and Technology Conference, ECTC 2010 - Las Vegas, NV, United States
Duration: Jun 1 2010Jun 4 2010

Publication series

NameProceedings - Electronic Components and Technology Conference
ISSN (Print)0569-5503

Other

Other60th Electronic Components and Technology Conference, ECTC 2010
CountryUnited States
CityLas Vegas, NV
Period6/1/106/4/10

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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