Routing Methodology for Minimizing Crosstalk in SoC

Takashi Yamada, Atsushi Sakai, Yoshifumi Matsushita, Hiroto Yasuura

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

In this paper, we propose new physical design techniques to reduce crosstalk noise and crosstalk-induced delay variations caused in a nanometer-scale system-on-a-chip (SoC). We have almost eliminated the coupling effect between signal wires by simply optimizing parameters for the automatic place and route methodology. Our approach consists of two techniques, (1) A 3-D optimization technique for tuning the routing grid configuration both in the horizontal and vertical directions. (2) A co-optimization technique for tuning the cell utilization ratio and the routing grid simultaneously. Experiments on the design of an image processing circuit fabricated in a 0.13μm CMOS process with six layers of copper interconnect show that crosstalk noise is almost eliminated. From the results of a static timing analysis considering the worst-case crosstalk condition, the longest path delay is decreased by about 15% maximum if technique (1) is used, and by about 7% maximum if technique (2) is used. The 7-15% delay reduction has been achieved without process improvement, and this reduction corresponds to between 1/4 and 1/2 generation of process progress.

Original languageEnglish
Pages (from-to)2347-2356
Number of pages10
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE86-A
Issue number9
Publication statusPublished - Sep 2003

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Crosstalk
Routing
Chip
Methodology
Optimization Techniques
Tuning
Grid
Timing Analysis
Process Improvement
Longest Path
Static Analysis
Interconnect
Copper
3D
Image Processing
Image processing
Horizontal
Atmospherics
Vertical
Wire

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Information Systems

Cite this

Routing Methodology for Minimizing Crosstalk in SoC. / Yamada, Takashi; Sakai, Atsushi; Matsushita, Yoshifumi; Yasuura, Hiroto.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E86-A, No. 9, 09.2003, p. 2347-2356.

Research output: Contribution to journalArticle

Yamada, Takashi ; Sakai, Atsushi ; Matsushita, Yoshifumi ; Yasuura, Hiroto. / Routing Methodology for Minimizing Crosstalk in SoC. In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2003 ; Vol. E86-A, No. 9. pp. 2347-2356.
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