Routing methodology for minimizing interconnect energy dissipation

Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura

Research output: Contribution to journalConference article

Abstract

In this paper, we propose a new physical design technique for sub-quarter micron system-on-a-chip (SoC). By optimizing the routing grid configuration for the automatic place and route methodology, coupling effects such as crosstalk noise and coupled energy dissipation are almost eliminated with only a small cost to the runtime. Experiments are performed on the design of an image processing circuit using a sub-quarter micron CMOS process with multi-layered interconnects. Simply by employing our proposed technique, net switching energy dissipation can be reduced by about 10% maximum without any area penalty. This significant energy reduction greatly accelerates the performance of SoCs.

Original languageEnglish
Pages (from-to)120-123
Number of pages4
JournalProceedings of the IEEE Great Lakes Symposium on VLSI
Publication statusPublished - 2003
EventProceedings of the 2003 ACM Great Lakes Symposium on VLSI - Washington, DC, United States
Duration: Apr 28 2003Apr 29 2003

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Routing methodology for minimizing interconnect energy dissipation'. Together they form a unique fingerprint.

  • Cite this