In this paper, we propose a new physical design technique for sub-quarter micron system-on-a-chip (SoC). By optimizing the routing grid configuration for the automatic place and route methodology, coupling effects such as crosstalk noise and coupled energy dissipation are almost eliminated with only a small cost to the runtime. Experiments are performed on the design of an image processing circuit using a sub-quarter micron CMOS process with multi-layered interconnects. Simply by employing our proposed technique, net switching energy dissipation can be reduced by about 10% maximum without any area penalty. This significant energy reduction greatly accelerates the performance of SoCs.
|Number of pages||4|
|Journal||Proceedings of the IEEE Great Lakes Symposium on VLSI|
|Publication status||Published - 2003|
|Event||Proceedings of the 2003 ACM Great Lakes Symposium on VLSI - Washington, DC, United States|
Duration: Apr 28 2003 → Apr 29 2003
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering